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1. general description nxp semiconductors designed the LPC2420/ 2460 microcontroller around a 16-bit/32-bit arm7tdmi-s cpu core with real-time debug interfaces that include both jtag and embedded trace. the LPC2420/ 2460 is flashless. the lpc2 420/2460 can execute both 32-bit arm and 16-bit thumb instructions. su pport for the two instruction sets means engineers can choose to optimize their applicat ion for either performance or code size at the sub-routine level. when the core executes instructions in thumb state it can reduce code size by more than 30 % with only a small loss in performance while executing instructions in arm state maximizes core performance. the LPC2420/2460 microcontroller is ideal for multi-purpose communication applications. it incorporates a 10/100 ethernet media ac cess controller (mac) (lpc2460 only), a usb full-speed device/host/otg controller with 4 kb of endpoint ram, four uarts, two controller area network (can) channels (lpc2460 only), an spi interface, two synchronous serial ports (ssp), three i 2 c interfaces, and an i 2 s interface. supporting this collection of serial communications interfaces are the following feature components; an on-chip 4 mhz internal precision oscillator, 82/98 kb of total ram consisting of 64 kb of local sram, 16 kb sram for ethernet (lpc2460 only), 16 kb sram for general purpose dma, 2 kb of battery powered sram, and an external memory controller (emc). these features make this device optimally suited for communication gateways and protocol converters. complementing th e many serial communication controllers, versatile clocking capabilitie s, and memory features are various 32-bit timers, an improved 10-bit adc, 10-bit dac, two pwm unit s, four external interrupt pins, and up to 160 fast gpio lines. the LPC2420/2460 connects 64 of the gpio pins to the hardware based vector interrupt contro ller (vic) that means these external inputs can generate edge-triggered interrupts. all of these feat ures make the LPC2420/2460 particularly suitable for industrial co ntrol and medical systems. 2. features ? arm7tdmi-s processor, running at up to 72 mhz. ? 82/98 kb on-chip sram includes: ? 64 kb of sram on the arm local bus for high performance cpu access. ? 16 kb sram for ethernet interface. can also be used as general purpose sram. (lpc2460 only) ? 16 kb sram for general purpose dma use also accessible by the usb. ? 2 kb sram data storage powered from the real-time clock (rtc) power domain. LPC2420/2460 flashless 16-bit/32-bit microc ontroller; ethernet, can, isp/iap, usb 2.0 device/host/otg , external memory interface rev. 05 ? 24 february 2010 preliminary data sheet
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 2 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? dual advanced high-performance bus (ahb) system allows simultaneous ethernet dma, and usb dma with no contention (lpc2460 only). ? emc provides support for asynchronous st atic memory devices such as ram, rom and flash, as well as dynamic memories such as single data rate sdram. ? advanced vectored interrupt controller (vic), supporting up to 32 vectored interrupts. ? general purpose dma controller (gpdma) on ahb that can be used with the ssp, i 2 s, and sd/mmc interface as well as for memory-to-memory transfers. ? serial interfaces: ? ethernet mac with mii/rmii interface and associated dma controller (lpc2460 only). these functions reside on an independent ahb. ? usb 2.0 full-speed dual port device/ho st/otg controller with on-chip phy and associated dma controller. ? four uarts with fractional baud rate generation, one with modem control i/o, one with irda support, all with fifo. ? can controller with two channels (lpc2460 only). ? spi controller. ? two ssp controllers, with fifo and multi-pr otocol capabilities. one is an alternate for the spi port, sharing it s interrupt. ssps can be used with the gpdma controller. ? three i 2 c-bus interfaces (one with open-drai n and two with standard port pins). ? i 2 s (inter-ic sound) interface for digital audio input or output. it can be used with the gpdma. ? other peripherals: ? sd/mmc memory card interface. ? 160 general purpose i/o pins with configurable pull-up/down resistors. ? 10-bit adc with input multiplexing among 8 pins. ? 10-bit dac. ? four general purpose timers/counters with 8 capture inputs and 10 compare outputs. each timer block has an external count input. ? two pwm/timer blocks with support for th ree-phase motor control. each pwm has an external count inputs. ? rtc with separate power domain. clock sour ce can be the rtc oscillator or the apb clock. ? 2 kb sram powered from the rtc power pin, allowing data to be stored when the rest of the chip is powered off. ? watchdog timer (wdt). the wdt can be cl ocked from the internal rc oscillator, the rtc oscillator, or the apb clock. ? standard arm test/debug interface for compatibility with existing tools. ? emulation trace module supports real-time trace. ? single 3.3 v power supply (3.0 v to 3.6 v). ? four reduced power modes: idle, sleep, power-down, and deep power-down. ? four external interrupt inputs configurable as edge/level sensitive. all pins on port 0 and port 2 can be used as edge sensitive interrupt sources. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, port 0/2 pin interrupt, ethernet wake-up interrupt (lpc2460 only), can bus activity (lpc2460 only)).
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 3 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? two independent power domains allow fine tuning of power consumption based on needed features. ? each peripheral has its own clock divider fo r further power saving. these dividers help reduce active power by 20 % to 30 %. ? brownout detect with separate thresholds for interrupt and forced reset. ? on-chip power-on reset. ? on-chip crystal oscillator wit h an operating range of 1 mhz to 24 mhz. ? 4 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. when used as the cpu clock, does not allow can and usb to run. ? on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the rtc oscillator. ? boundary scan for simplified board testing. ? versatile pin function selections allow mo re possibilities for us ing on-chip peripheral functions. 3. applications ? industrial control ? medical systems ? protocol converter ? communications 4. ordering information table 1. ordering information type number package name description version LPC2420fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 LPC2420fet208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm sot950-1 lpc2460fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 lpc2460fet208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm sot950-1
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 4 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 4.1 ordering options table 2. ordering options type number flash (kb) sram (kb) external bus ethernet usb otg/ ohci/ device + 4 kb fifo can channels sd/ mmc gp dma adc channels dac channels temp range local bus ethernet buffer gp/usb rtc total LPC2420fbd208 n/a 64 - 16 2 82 full 32-bit - yes - yes yes 8 1 ? 40 c to +85 c LPC2420fet208 n/a 64 16 16 2 98 full 32-bit mii/rmii yes 2 yes yes 8 1 ? 40 c to +85 c lpc2460fbd208 n/a 64 16 16 2 98 full 32-bit mii/rmii yes 2 yes yes 8 1 ? 40 c to +85 c lpc2460fet208 n/a 64 16 16 2 98 full 32-bit mii/rmii yes 2 yes yes 8 1 ? 40 c to +85 c
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 5 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 5. block diagram (1) lpc2460 only. fig 1. LPC2420/2460 block diagram power domain 2 LPC2420/2460 a[23:0] d[31:0] external memory controller alarm 002aad313 pwm0, pwm1 arm7tdmi-s pll eint3 to eint0 p3, p4 p0, p1, p2, legacy gpi/o 64 pins total p0, p1 sck, sck0 mosi, mosi0 ssel, ssel0 sck1 mosi1 miso1 ssel1 scl0, scl1, scl2 i2srx_clk i2stx_clk i2srx_ws i2stx_ws 8 ad0 rtcx1 rtcx2 mciclk, mcipwr rxd0, rxd2, rxd3 txd1 rxd1 rd1, rd2 td1, td2 can1 (1) , can2 (1) port1 xtal1 tck tdo extin0 xtal2 reset trst tdi tms high-speed gpi/o 160 pins total port2 64 kb sram internal sram controller test/debug interface emulation trace module trace signals ahb bridge ahb bridge ethernet mac with dma (1) 16 kb sram (1) master port ahb to ahb bridge slave port system clock system functions internal rc oscillator v dda v dd(3v3) v dd(dcdc)(3v3) vref v ssa , v sscore , v ssio vic 16 kb sram usb device/ host/otg with 4 kb ram and dma gp dma controller i 2 s interface spi, ssp0 interface i2srx_sda i2stx_sda miso, miso0 ssp1 interface sd/mmc card interface mcicmd, mcidat[3:0] txd0, txd2, txd3 uart0, uart2, uart3 uart1 dtr1, rts1 dsr1, cts1, dcd1, ri1 i 2 c0, i 2 c1, i 2 c2 sda0, sda1, sda2 external interrupts capture/compare timer0/timer1/ timer2/timer3 a/d converter d/a converter 2 kb battery ram rtc oscillator real- time clock watchdog timer system control 2 cap0/cap1/ cap2/cap3 4 mat2/mat3, 2 mat0, 3 mat1 6 pwm0/pwm1 1 pcap0, 2 pcap1 aout vbat ahb to apb bridge mii/rmii v bus dbgen p0, p2 ahb2 ahb1 control lines
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 6 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 6. pinning information 6.1 pinning fig 2. LPC2420/2460 pinning lqfp208 package LPC2420fbd208 lpc2460fbd208 156 53 104 208 157 105 1 52 002aad31 4 fig 3. LPC2420/2460 pinning tfbga208 package 002aad31 5 LPC2420fet208 lpc2460fet208 transparent top view ball a1 index area u t r p n m k h l j g f e d c a b 24681012 13 14 15 17 16 1357911 table 3. pin allocation table pin symbol pin symbol pin symbol pin symbol row a 1 p3[27]/d27/ cap1[0]/pwm1[4] 2 v ssio 3 p1[0]/enet_txd0 4 p4[31]/ cs1 5 p1[4]/enet_tx_en 6 p1[9]/enet_rxd0 7 p1[14]/enet_rx_er 8 p1[15]/ enet_ref_clk/ enet_rx_clk 9 p1[17]/enet_mdio 10 p1[3]/enet_txd3/ mcicmd/pwm0[2] 11 p4[15]/a15 12 v ssio 13 p3[20]/d20/ pwm0[5]/dsr1 14 p1[11]/enet_rxd2/ mcidat2/pwm0[6] 15 p0[8]/i2stx_ws/ miso1/mat2[2] 16 p1[12]/enet_rxd3/ mcidat3/pcap0[0]
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 7 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 17 p1[5]/enet_tx_er/ mcipwr/pwm0[3] - - - row b 1 p3[2]/d2 2 p3[10]/d10 3 p3[1]/d1 4 p3[0]/d0 5 p1[1]/enet_txd1 6 v ssio 7 p4[30]/ cs0 8 p4[24]/ oe 9 p4[25]/ we 10 p4[29]/ bls3 / mat2[1]/rxd3 11 p1[6]/enet_tx_clk/ mcidat0/pwm0[4] 12 p0[4]/i2srx_clk/rd2/ cap2[0] 13 v dd(3v3) 14 p3[19]/d19/ pwm0[4]/dcd1 15 p4[14]/a14 16 p4[13]/a13 17 p2[0]/pwm1[1]/txd1/ traceclk - - - row c 1 p3[13]/d13 2 tdi 3 rtck 4 p0[2]/txd0 5 p3[9]/d9 6 p3[22]/d22/ pcap0[0]/ri1 7 p1[8]/enet_crs_dv/ enet_crs 8 p1[10]/enet_rxd1 9 v dd(3v3) 10 p3[21]/d21/ pwm0[6]/dtr1 11 p4[28]/ bls2 / mat2[0]/txd3 12 p0[5]/i2srx_ws/td2/ cap2[1] 13 p0[7]/i2stx_clk/sck1 /mat2[1] 14 p0[9]/i2stx_sda/ mosi1/mat2[3] 15 p3[18]/d18/ pwm0[3]/cts1 16 p4[12]/a12 17 v dd(3v3) - - - row d 1 trst 2 p3[28]/d28/ cap1[1]/pwm1[5] 3 tdo 4 p3[12]/d12 5 p3[11]/d11 6 p0[3]/rxd0 7 v dd(3v3) 8 p3[8]/d8 9 p1[2]/enet_txd2/ mciclk/pwm0[1] 10 p1[16]/enet_mdc 11 v dd(dcdc)(3v3) 12 v sscore 13 p0[6]/i2srx_sda/ ssel1/mat2[0] 14 p1[7]/enet_col/ mcidat1/pwm0[5] 15 p2[2]/pwm1[3]/ cts1/pipestat1 16 p1[13]/enet_rx_dv 17 p2[4]/pwm1[5]/ dsr1/tracesync - - - row e 1 p0[26]/ad0[3]/ aout/rxd3 2 tck 3 tms 4 p3[3]/d3 14 p2[1]/pwm1[2]/rxd1/ pipestat0 15 v ssio 16 p2[3]/pwm1[4]/ dcd1/pipestat2 17 p2[6]/pcap1[0]/ ri1/tracepkt1 row f 1 p0[25]/ad0[2]/ i2srx_sda/txd3 2 p3[4]/d4 3 p3[29]/d29/ mat1[0]/pwm1[6] 4 dbgen 14 p4[11]/a11 15 p3[17]/d17/ pwm0[2]/rxd1 16 p2[5]/pwm1[6]/ dtr1/tracepkt0 17 p3[16]/d16/ pwm0[1]/txd1 row g 1 p3[5]/d5 2 p0[24]/ad0[1]/ i2srx_ws/cap3[1] 3 v dd(3v3) 4 v dda 14 n.c. 15 p4[27]/ bls1 16 p2[7]/rd2/ rts1/tracepkt2 17 p4[10]/a10 table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 8 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller row h 1 p0[23]/ad0[0]/ i2srx_clk/cap3[0] 2 p3[14]/d14 3 p3[30]/d30/ mat1[1]/rts1 4 v dd(dcdc)(3v3) 14 v ssio 15 p2[8]/td2/ txd2/tracepkt3 16 p2[9]/ usb_connect1/ rxd2/extin0 17 p4[9]/a9 row j 1 p3[6]/d6 2 v ssa 3 p3[31]/d31/mat1[2] 4 n.c. 14 p0[16]/rxd1/ ssel0/ssel 15 p4[23]/a23/ rxd2/mosi1 16 p0[15]/txd1/ sck0/sck 17 p4[8]/a8 row k 1 vref 2 rtcx1 3 rstout 4 v sscore 14 p4[22]/a22/ txd2/miso1 15 p0[18]/dcd1/ mosi0/mosi 16 v dd(3v3) 17 p0[17]/cts1/ miso0/miso row l 1 p3[7]/d7 2 rtcx2 3 v ssio 4 p2[30]/dqmout2/ mat3[2]/sda2 14 n.c. 15 p4[26]/ bls0 16 p4[7]/a7 17 p0[19]/dsr1/ mciclk/sda1 row m 1 p3[15]/d15 2 reset 3 vbat 4 xtal1 14 p4[6]/a6 15 p4[21]/a21/ scl2/ssel1 16 p0[21]/ri1/ mcipwr/rd1 17 p0[20]/dtr1/ mcicmd/scl1 row n 1 alarm 2 p2[31]/dqmout3/ mat3[3]/scl2 3 p2[29]/dqmout1 4 xtal2 14 p2[12]/ eint2 / mcidat2/i2stx_ws 15 p2[10]/ eint0 16 v ssio 17 p0[22]/rts1/ mcidat0/td1 row p 1 p1[31]/ usb_ovrcr2 / sck1/ad0[5] 2 p1[30]/usb_pwrd2/ v bus /ad0[4] 3 p2[27]/ckeout3/ mat3[1]/mosi0 4 p2[28]/dqmout0 5 p2[24]/ckeout0 6 v dd(3v3) 7 p1[18]/usb_up_led1/ pwm1[1]/cap1[0] 8 v dd(3v3) 9 p1[23]/usb_rx_dp1/ pwm1[4]/miso0 10 v sscore 11 v dd(dcdc)(3v3) 12 v ssio 13 p2[15]/ cs3 / cap2[1]/scl1 14 p4[17]/a17 15 p4[18]/a18 16 p4[19]/a19 17 v dd(3v3) - - - row r 1 p0[12]/ usb_ppwr2 / miso1/ad0[6] 2 p0[13]/usb_up_led2/ mosi1/ad0[7] 3 p0[28]/scl0 4 p2[25]/ckeout1 5 p3[24]/d24/ cap0[1]/pwm1[1] 6 p0[30]/usb_d ? 1 7 p2[19]/clkout1 8 p1[21]/usb_tx_dm1/ pwm1[3]/ssel0 9 v ssio 10 p1[26]/ usb_sspnd1 / pwm1[6]/cap0[0] 11 p2[16]/ cas 12 p2[14]/ cs2 / cap2[0]/sda1 table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 9 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 6.2 pin description 13 p2[17]/ ras 14 p0[11]/rxd2/scl2/ mat3[1] 15 p4[4]/a4 16 p4[5]/a5 17 p4[20]/a20/ sda2/sck1 - - - row t 1 p0[27]/sda0 2 p0[31]/usb_d+2 3 p3[26]/d26/ mat0[1]/pwm1[3] 4 p2[26]/ckeout2/ mat3[0]/miso0 5 v ssio 6 p3[23]/d23/ cap0[0]/pcap1[0] 7 p0[14]/ usb_hsten2 / usb_connect2/ ssel1 8 p2[20]/ dycs0 9 p1[24]/usb_rx_dm1/ pwm1[5]/mosi0 10 p1[25]/ usb_ls1 / usb_hsten1 /mat1[1] 11 p4[2]/a2 12 p1[27]/ usb_int1 / usb_ovrcr1 /cap0[1] 13 p1[28]/usb_scl1/ pcap1[0]/mat0[0] 14 p0[1]/td1/rxd3/scl1 15 p0[10]/txd2/sda2/ mat3[0] 16 p2[13]/ eint3 / mcidat3/i2stx_sda 17 p2[11]/ eint1 / mcidat1/i2stx_clk - - - row u 1 usb_d ? 2 2 p3[25]/d25/ mat0[0]/pwm1[2] 3 p2[18]/clkout0 4 p0[29]/usb_d+1 5 p2[23]/ dycs3 / cap3[1]/ssel0 6 p1[19]/ usb_tx_e1 / usb_ppwr1 /cap1[1] 7 p1[20]/usb_tx_dp1/ pwm1[2]/sck0 8 p1[22]/usb_rcv1/ usb_pwrd1/mat1[0] 9 p4[0]/a0 10 p4[1]/a1 11 p2[21]/ dycs1 12 p2[22]/ dycs2 / cap3[0]/sck0 13 v dd(3v3) 14 p1[29]/usb_sda1/ pcap1[1]/mat0[1] 15 p0[0]/rd1/txd3/sda1 16 p4[3]/a3 17 p4[16]/a16 - - - table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol table 4. pin description symbol pin ball type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. p0[0]/rd1/ txd3/sda1 94 [1] u15 [1] i/o p0[0] ? general purpose digital input/output pin. i rd1 ? can1 receiver input (lpc2460 only). o txd3 ? transmitter output for uart3. i/o sda1 ? i 2 c1 data input/output (this is not an open-drain pin). p0[1]/td1/rxd3/ scl1 96 [1] t14 [1] i/o p0[1] ? general purpose digital input/output pin. o td1 ? can1 transmitter output (lpc2460 only). i rxd3 ? receiver input for uart3. i/o scl1 ? i 2 c1 clock input/output (this is not an open-drain pin). p0[2]/txd0 202 [1] c4 [1] i/o p0[2] ? general purpose digital input/output pin. o txd0 ? transmitter output for uart0.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 10 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p0[3]/rxd0 204 [1] d6 [1] i/o p0[3] ? general purpose digital input/output pin. i rxd0 ? receiver input for uart0. p0[4]/ i2srx_clk/ rd2/cap2[0] 168 [1] b12 [1] i/o p0[4] ? general purpose digital input/output pin. i/o i2srx_clk ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i rd2 ? can2 receiver input (lpc2460 only). i cap2[0] ? capture input for timer 2, channel 0. p0[5]/ i2srx_ws/ td2/cap2[1] 166 [1] c12 [1] i/o p0[5] ? general purpose digital input/output pin. i/o i2srx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o td2 ? can2 transmitter output (lpc2460 only). i cap2[1] ? capture input for timer 2, channel 1. p0[6]/ i2srx_sda/ ssel1/mat2[0] 164 [1] d13 [1] i/o p0[6] ? general purpose digital input/output pin. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o ssel1 ? slave select for ssp1. o mat2[0] ? match output for timer 2, channel 0. p0[7]/ i2stx_clk/ sck1/mat2[1] 162 [1] c13 [1] i/o p0[7] ? general purpose digital input/output pin. i/o i2stx_clk ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i/o sck1 ? serial clock for ssp1. o mat2[1] ? match output for timer 2, channel 1. p0[8]/ i2stx_ws/ miso1/mat2[2] 160 [1] a15 [1] i/o p0[8] ? general purpose digital input/output pin. i/o i2stx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o miso1 ? master in slave out for ssp1. o mat2[2] ? match output for timer 2, channel 2. p0[9]/ i2stx_sda/ mosi1/mat2[3] 158 [1] c14 [1] i/o p0[9] ? general purpose digital input/output pin. i/o i2stx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o mosi1 ? master out slave in for ssp1. o mat2[3] ? match output for timer 2, channel 3. p0[10]/txd2/ sda2/mat3[0] 98 [1] t15 [1] i/o p0[10] ? general purpose digital input/output pin. o txd2 ? transmitter output for uart2. i/o sda2 ? i 2 c2 data input/output (this is not an open-drain pin). o mat3[0] ? match output for timer 3, channel 0. p0[11]/rxd2/ scl2/mat3[1] 100 [1] r14 [1] i/o p0[11] ? general purpose digi tal input/output pin. i rxd2 ? receiver input for uart2. i/o scl2 ? i 2 c2 clock input/output (this is not an open-drain pin). o mat3[1] ? match output for timer 3, channel 1. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 11 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p0[12]/ usb_ppwr2 / miso1/ad0[6] 41 [2] r1 [2] i/o p0[12] ? general purpose digital input/output pin. o usb_ppwr2 ? port power enable signal for usb port 2. i/o miso1 ? master in slave out for ssp1. i ad0[6] ? a/d converter 0, input 6. p0[13]/ usb_up_led2/ mosi1/ad0[7] 45 [2] r2 [2] i/o p0[13] ? general purpose digital input/output pin. o usb_up_led2 ? usb port 2 goodlink led indicator. it is low when device is configured (non-control endpoi nts enabled). it is high when the device is not configured or during global suspend. i/o mosi1 ? master out slave in for ssp1. i ad0[7] ? a/d converter 0, input 7. p0[14]/ usb_hsten2 / usb_connect2/ ssel1 69 [1] t7 [1] i/o p0[14] ? general purpose digital input/output pin. o usb_hsten2 ? host enabled status for usb port 2. o usb_connect2 ? softconnect control for usb port 2. signal used to switch an external 1.5 k resistor under software control. used with the softconnect usb feature. i/o ssel1 ? slave select for ssp1. p0[15]/txd1/ sck0/sck 128 [1] j16 [1] i/o p0[15] ? general purpose digital input/output pin. o txd1 ? transmitter output for uart1. i/o sck0 ? serial clock for ssp0. i/o sck ? serial clock for spi. p0[16]/rxd1/ ssel0/ssel 130 [1] j14 [1] i/o p0 [16] ? general purpose digital input/output pin. i rxd1 ? receiver input for uart1. i/o ssel0 ? slave select for ssp0. i/o ssel ? slave select for spi. p0[17]/cts1/ miso0/miso 126 [1] k17 [1] i/o p0[17] ? general purpose digital input/output pin. i cts1 ? clear to send input for uart1. i/o miso0 ? master in slave out for ssp0. i/o miso ? master in slave out for spi. p0[18]/dcd1/ mosi0/mosi 124 [1] k15 [1] i/o p0[18] ? general purpose digital input/output pin. i dcd1 ? data carrier detect input for uart1. i/o mosi0 ? master out slave in for ssp0. i/o mosi ? master out slave in for spi. p0[19]/dsr1/ mciclk/sda1 122 [1] l17 [1] i/o p0[19] ? general purpose digital input/output pin. i dsr1 ? data set ready input for uart1. o mciclk ? clock output line for sd/mmc interface. i/o sda1 ? i 2 c1 data input/output (this is not an open-drain pin). p0[20]/dtr1/ mcicmd/scl1 120 [1] m17 [1] i/o p0[20] ? general purpose digital input/output pin. o dtr1 ? data terminal ready output for uart1. i/o mcicmd ? command line for sd/mmc interface. i/o scl1 ? i 2 c1 clock input/output (this is not an open-drain pin). table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 12 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p0[21]/ri1/ mcipwr/rd1 118 [1] m16 [1] i/o p0[21] ? general purpose digital input/output pin. i ri1 ? ring indicator input for uart1. o mcipwr ? power supply enable for external sd/mmc power supply. i rd1 ? can1 receiver input (lpc2460 only). p0[22]/rts1/ mcidat0/td1 116 [1] n17 [1] i/o p0[22] ? general purpose digital input/output pin. o rts1 ? request to send output for uart1. i/o mcidat0 ? data line 0 for sd/mmc interface. o td1 ? can1 transmitter output (lpc2460 only). p0[23]/ad0[0]/ i2srx_clk/ cap3[0] 18 [2] h1 [2] i/o p0[23] ? general purpose digital input/output pin. i ad0[0] ? a/d converter 0, input 0. i/o i2srx_clk ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i cap3[0] ? capture input for timer 3, channel 0. p0[24]/ad0[1]/ i2srx_ws/ cap3[1] 16 [2] g2 [2] i/o p0[24] ? general purpose digital input/output pin. i ad0[1] ? a/d converter 0, input 1. i/o i2srx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i cap3[1] ? capture input for timer 3, channel 1. p0[25]/ad0[2]/ i2srx_sda/ txd3 14 [2] f1 [2] i/o p0[25] ? general purpose digital input/output pin. i ad0[2] ? a/d converter 0, input 2. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o txd3 ? transmitter output for uart3. p0[26]/ad0[3]/ aout/rxd3 12 [2] [3] e1 [2] [3] i/o p0[26] ? general purpose digital input/output pin. i ad0[3] ? a/d converter 0, input 3. o aout ? d/a converter output. i rxd3 ? receiver input for uart3. p0[27]/sda0 50 [4] t1 [4] i/o p0[27] ? general purpose digital input/output pin. i/o sda0 ? i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). p0[28]/scl0 48 [4] r3 [4] i/o p0[28] ? general purpose digital input/output pin. i/o scl0 ? i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). p0[29]/usb_d+1 61 [5] u4 [5] i/o p0[29] ? general purpose digital input/output pin. i/o usb_d+1 ? usb port 1 bidirectional d+ line. p0[30]/usb_d ? 1 62 [5] r6 [5] i/o p0[30] ? general purpose digital input/output pin. i/o usb_d ? 1 ? usb port 1 bidirectional d ? line. p0[31]/usb_d+2 51 [5] t2 [5] i/o p0[31] ? general purpose digital input/output pin. i/o usb_d+2 ? usb port 2 bidirectional d+ line. p1[0] to p1[31] i/o port 1: port 1 is a 32 bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 13 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p1[0]/ enet_txd0 196 [1] a3 [1] i/o p1[0] ? general purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0 (rm ii/mii interface) (lpc2460 only). p1[1]/ enet_txd1 194 [1] b5 [1] i/o p1[1] ? general purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1 (rm ii/mii interface) (lpc2460 only). p1[2]/ enet_txd2/ mciclk/ pwm0[1] 185 [1] d9 [1] i/o p1[2] ? general purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface) (lpc2460 only). o mciclk ? clock output line for sd/mmc interface. o pwm0[1] ? pulse width modulator 0, output 1. p1[3]/ enet_txd3/ mcicmd/ pwm0[2] 177 [1] a10 [1] i/o p1[3] ? general purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface) (lpc2460 only). i/o mcicmd ? command line for sd/mmc interface. o pwm0[2] ? pulse width modulator 0, output 2. p1[4]/ enet_tx_en 192 [1] a5 [1] i/o p1[4] ? general purpose digital input/output pin. o enet_tx_en ? ethernet transmit data enable (rmii/mii interface) (lpc2460 only). p1[5]/ enet_tx_er/ mcipwr/ pwm0[3] 156 [1] a17 [1] i/o p1[5] ? general purpose digital input/output pin. o enet_tx_er ? ethernet transmit error (mii interface) (lpc2460 only). o mcipwr ? power supply enable for external sd/mmc power supply. o pwm0[3] ? pulse width modulator 0, output 3. p1[6]/ enet_tx_clk/ mcidat0/ pwm0[4] 171 [1] b11 [1] i/o p1[6] ? general purpose digital input/output pin. i enet_tx_clk ? ethernet transmit clock (mii interface) (lpc2460 only). i/o mcidat0 ? data line 0 for sd/mmc interface. o pwm0[4] ? pulse width modulator 0, output 4. p1[7]/ enet_col/ mcidat1/ pwm0[5] 153 [1] d14 [1] i/o p1[7] ? general purpose digital input/output pin. i enet_col ? ethernet collision detect (mii interface) (lpc2460 only). i/o mcidat1 ? data line 1 for sd/mmc interface. o pwm0[5] ? pulse width modulator 0, output 5. p1[8]/ enet_crs_dv/ enet_crs 190 [1] c7 [1] i/o p1[8] ? general purpose digital input/output pin. i enet_crs_dv/enet_crs ? ethernet carrier sense/data valid (rmii interface)/ ethernet carrier sense (mii interface) (lpc2460 only). p1[9]/ enet_rxd0 188 [1] a6 [1] i/o p1[9] ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0 (rmi i/mii interface) (lpc2460 only). p1[10]/ enet_rxd1 186 [1] c8 [1] i/o p1[10] ? general purpose digital input/output pin. i enet_rxd1 ? ethernet receive data 1 (rmi i/mii interface) (lpc2460 only). p1[11]/ enet_rxd2/ mcidat2/ pwm0[6] 163 [1] a14 [1] i/o p1[11] ? general purpose digi tal input/output pin. i enet_rxd2 ? ethernet receive data 2 (mii interface) (lpc2460 only). i/o mcidat2 ? data line 2 for sd/mmc interface. o pwm0[6] ? pulse width modulator 0, output 6. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 14 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p1[12]/ enet_rxd3/ mcidat3/ pcap0[0] 157 [1] a16 [1] i/o p1[12] ? general purpose digital input/output pin. i enet_rxd3 ? ethernet receive data (mii interface) (lpc2460 only). i/o mcidat3 ? data line 3 for sd/mmc interface. i pcap0[0] ? capture input for pwm0, channel 0. p1[13]/ enet_rx_dv 147 [1] d16 [1] i/o p1[13] ? general purpose digital input/output pin. i enet_rx_dv ? ethernet receive data valid (mii interface) (lpc2460 only). p1[14]/ enet_rx_er 184 [1] a7 [1] i/o p1[14] ? general purpose digital input/output pin. i enet_rx_er ? ethernet receive error (rmi i/mii interface) (lpc2460 only). p1[15]/ enet_ref_clk/ enet_rx_clk 182 [1] a8 [1] i/o p1[15] ? general purpose digital input/output pin. i enet_ref_clk/enet_rx_clk ? ethernet reference clock (rmii interface)/ ethernet receive clock (mii interface) (lpc2460 only). p1[16]/ enet_mdc 180 [1] d10 [1] i/o p1[16] ? general purpose digital input/output pin. o enet_mdc ? ethernet miim clock (lpc2460 only). p1[17]/ enet_mdio 178 [1] a9 [1] i/o p1[17] ? general purpose digital input/output pin. i/o enet_mdio ? ethernet miim data input and output (lpc2460 only). p1[18]/ usb_up_led1/ pwm1[1]/ cap1[0] 66 [1] p7 [1] i/o p1[18] ? general purpose digital input/output pin. o usb_up_led1 ? usb port 1 goodlink led indicator. it is low when device is configured (non-control endpoi nts enabled). it is high when the device is not configured or during global suspend. o pwm1[1] ? pulse width modulator 1, channel 1 output. i cap1[0] ? capture input for timer 1, channel 0. p1[19]/ usb_tx_e1 / usb_ppwr1 / cap1[1] 68 [1] u6 [1] i/o p1[19] ? general purpose digital input/output pin. o usb_tx_e1 ? transmit enable signal for usb port 1 (otg transceiver). o usb_ppwr1 ? port power enable signal for usb port 1. i cap1[1] ? capture input for timer 1, channel 1. p1[20]/ usb_tx_dp1/ pwm1[2]/sck0 70 [1] u7 [1] i/o p1[20] ? general purpose digital input/output pin. o usb_tx_dp1 ? d+ transmit data for usb port 1 (otg transceiver). o pwm1[2] ? pulse width modulator 1, channel 2 output. i/o sck0 ? serial clock for ssp0. p1[21]/ usb_tx_dm1/ pwm1[3]/ssel0 72 [1] r8 [1] i/o p1[21] ? general purpose digital input/output pin. o usb_tx_dm1 ? d ? transmit data for usb port 1 (otg transceiver). o pwm1[3] ? pulse width modulator 1, channel 3 output. i/o ssel0 ? slave select for ssp0. p1[22]/ usb_rcv1/ usb_pwrd1/ mat1[0] 74 [1] u8 [1] i/o p1[22] ? general purpose digital input/output pin. i usb_rcv1 ? differential receive data for usb port 1 (otg transceiver). i usb_pwrd1 ? power status for usb port 1 (host power switch). o mat1[0] ? match output for timer 1, channel 0. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 15 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p1[23]/ usb_rx_dp1/ pwm1[4]/miso0 76 [1] p9 [1] i/o p1[23] ? general purpose digital input/output pin. i usb_rx_dp1 ? d+ receive data for usb port 1 (otg transceiver). o pwm1[4] ? pulse width modulator 1, channel 4 output. i/o miso0 ? master in slave out for ssp0. p1[24]/ usb_rx_dm1/ pwm1[5]/mosi0 78 [1] t9 [1] i/o p1[24] ? general purpose digital input/output pin. i usb_rx_dm1 ? d ? receive data for usb po rt 1 (otg transceiver). o pwm1[5] ? pulse width modulator 1, channel 5 output. i/o mosi0 ? master out slave in for ssp0. p1[25]/ usb_ls1 / usb_hsten1 / mat1[1] 80 [1] t10 [1] i/o p1[25] ? general purpose digital input/output pin. o usb_ls1 ? low-speed status for usb port 1 (otg transceiver). o usb_hsten1 ? host enabled status for usb port 1. o mat1[1] ? match output for timer 1, channel 1. p1[26]/ usb_sspnd1 / pwm1[6]/ cap0[0] 82 [1] r10 [1] i/o p1[26] ? general purpose digital input/output pin. o usb_sspnd1 ? usb port 1 bus suspend status (otg transceiver). o pwm1[6] ? pulse width modulator 1, channel 6 output. i cap0[0] ? capture input for timer 0, channel 0. p1[27]/ usb_int1 / usb_ovrcr1 / cap0[1] 88 [1] t12 [1] i/o p1[27] ? general purpose digital input/output pin. i usb_int1 ? usb port 1 otg transceiver interrupt (otg transceiver). i usb_ovrcr1 ? usb port 1 over-current status. i cap0[1] ? capture input for timer 0, channel 1. p1[28]/ usb_scl1/ pcap1[0]/ mat0[0] 90 [1] t13 [1] i/o p1[28] ? general purpose digital input/output pin. i/o usb_scl1 ? usb port 1 i 2 c-bus serial clock (otg transceiver). i pcap1[0] ? capture input for pwm1, channel 0. o mat0[0] ? match output for timer 0, channel 0. p1[29]/ usb_sda1/ pcap1[1]/ mat0[1] 92 [1] u14 [1] i/o p1[29] ? general purpose digital input/output pin. i/o usb_sda1 ? usb port 1 i 2 c-bus serial data (otg transceiver). i pcap1[1] ? capture input for pwm1, channel 1. o mat0[1] ? match output for timer 0, channel 0. p1[30]/ usb_pwrd2/ v bus /ad0[4] 42 [2] p2 [2] i/o p1[30] ? general purpose digital input/output pin. i usb_pwrd2 ? power status for usb port 2. i v bus ? monitors the presence of usb bus power. note: this signal must be high for usb reset to occur. i ad0[4] ? a/d converter 0, input 4. p1[31]/ usb_ovrcr2 / sck1/ad0[5] 40 [2] p1 [2] i/o p1[31] ? general purpose digital input/output pin. i usb_ovrcr2 ? over-current status for usb port 2. i/o sck1 ? serial clock for ssp1. i ad0[5] ? a/d converter 0, input 5. p2[0] to p2[31] i/o port 2: port 2 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 16 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p2[0]/pwm1[1]/ txd1/ traceclk 154 [1] b17 [1] i/o p2[0] ? general purpose digital input/output pin. o pwm1[1] ? pulse width modulator 1, channel 1 output. o txd1 ? transmitter output for uart1. o traceclk ? trace clock. p2[1]/pwm1[2]/ rxd1/ pipestat0 152 [1] e14 [1] i/o p2[1] ? general purpose digital input/output pin. o pwm1[2] ? pulse width modulator 1, channel 2 output. i rxd1 ? receiver input for uart1. o pipestat0 ? pipeline status, bit 0. p2[2]/pwm1[3]/ cts1/ pipestat1 150 [1] d15 [1] i/o p2[2] ? general purpose digital input/output pin. o pwm1[3] ? pulse width modulator 1, channel 3 output. i cts1 ? clear to send input for uart1. o pipestat1 ? pipeline status, bit 1. p2[3]/pwm1[4]/ dcd1/ pipestat2 144 [1] e16 [1] i/o p2[3] ? general purpose digital input/output pin. o pwm1[4] ? pulse width modulator 1, channel 4 output. i dcd1 ? data carrier detect input for uart1. o pipestat2 ? pipeline status, bit 2. p2[4]/pwm1[5]/ dsr1/ tracesync 142 [1] d17 [1] i/o p2[4] ? general purpose digital input/output pin. o pwm1[5] ? pulse width modulator 1, channel 5 output. i dsr1 ? data set ready input for uart1. o tracesync ? trace synchronization. p2[5]/pwm1[6]/ dtr1/ tracepkt0 140 [1] f16 [1] i/o p2[5] ? general purpose digital input/output pin. o pwm1[6] ? pulse width modulator 1, channel 6 output. o dtr1 ? data terminal ready output for uart1. o tracepkt0 ? trace packet, bit 0. p2[6]/pcap1[0]/ ri1/tracepkt1 138 [1] e17 [1] i/o p2[6] ? general purpose digital input/output pin. i pcap1[0] ? capture input for pwm1, channel 0. i ri1 ? ring indicator input for uart1. o tracepkt1 ? trace packet, bit 1. p2[7]/rd2/ rts1/ tracepkt2 136 [1] g16 [1] i/o p2[7] ? general purpose digital input/output pin. i rd2 ? can2 receiver input (lpc2460 only). o rts1 ? request to send output for uart1. o tracepkt2 ? trace packet, bit 2. p2[8]/td2/ txd2/ tracepkt3 134 [1] h15 [1] i/o p2[8] ? general purpose digital input/output pin. o td2 ? can2 transmitter output (lpc2460 only). o txd2 ? transmitter output for uart2. o tracepkt3 ? trace packet, bit 3. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 17 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p2[9]/ usb_connect1/ rxd2/ extin0 132 [1] h16 [1] i/o p2[9] ? general purpose digital input/output pin. o usb_connect1 ? usb1 softconnect control. signal used to switch an external 1.5 k resistor under the softwa re control. used with the softconnect usb feature. i rxd2 ? receiver input for uart2. i extin0 ? external trigger input. p2[10]/ eint0 110 [6] n15 [6] i/o p2[10] ? general purpose digital input/output pin. note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after a reset. i eint0 ? external interrupt 0 input. p2[11]/ eint1 / mcidat1/ i2stx_clk 108 [6] t17 [6] i/o p2[11] ? general purpose digi tal input/output pin. i eint1 ? external interrupt 1 input. i/o mcidat1 ? data line 1 for sd/mmc interface. i/o i2stx_clk ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . p2[12]/ eint2 / mcidat2/ i2stx_ws 106 [6] n14 [6] i/o p2[12] ? general purpose digital input/output pin. i eint2 ? external interrupt 2 input. i/o mcidat2 ? data line 2 for sd/mmc interface. i/o i2stx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . p2[13]/ eint3 / mcidat3/ i2stx_sda 102 [6] t16 [6] i/o p2[13] ? general purpose digital input/output pin. i eint3 ? external interrupt 3 input. i/o mcidat3 ? data line 3 for sd/mmc interface. i/o i2stx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . p2[14]/ cs2 / cap2[0]/sda1 91 [6] r12 [6] i/o p2[14] ? general purpose digital input/output pin. o cs2 ? low active chip select 2 signal. i cap2[0] ? capture input for timer 2, channel 0. i/o sda1 ? i 2 c1 data input/output (this is not an open-drain pin). p2[15]/ cs3 / cap2[1]/scl1 99 [6] p13 [6] i/o p2[15] ? general purpose digital input/output pin. o cs3 ? low active chip select 3 signal. i cap2[1] ? capture input for timer 2, channel 1. i/o scl1 ? i 2 c1 clock input/output (this is not an open-drain pin). p2[16]/ cas 87 [1] r11 [1] i/o p2[16] ? general purpose digital input/output pin. o cas ? low active sdram column address strobe. p2[17]/ ras 95 [1] r13 [1] i/o p2[17] ? general purpose digital input/output pin. o ras ? low active sdram row address strobe. p2[18]/ clkout0 59 [1] u3 [1] i/o p2[18] ? general purpose digital input/output pin. o clkout0 ? sdram clock 0. p2[19]/ clkout1 67 [1] r7 [1] i/o p2[19] ? general purpose digital input/output pin. o clkout1 ? sdram clock 1. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 18 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p2[20]/ dycs0 73 [1] t8 [1] i/o p2[20] ? general purpose digital input/output pin. o dycs0 ? sdram chip select 0. p2[21]/ dycs1 81 [1] u11 [1] i/o p2[21] ? general purpose digital input/output pin. o dycs1 ? sdram chip select 1. p2[22]/ dycs2 / cap3[0]/sck0 85 [1] u12 [1] i/o p2[22] ? general purpose digital input/output pin. o dycs2 ? sdram chip select 2. i cap3[0] ? capture input for timer 3, channel 0. i/o sck0 ? serial clock for ssp0. p2[23]/ dycs3 / cap3[1]/ssel0 64 [1] u5 [1] i/o p2[23] ? general purpose digital input/output pin. o dycs3 ? sdram chip select 3. i cap3[1] ? capture input for timer 3, channel 1. i/o ssel0 ? slave select for ssp0. p2[24]/ ckeout0 53 [1] p5 [1] i/o p2[24] ? general purpose digital input/output pin. o ckeout0 ? sdram clock enable 0. p2[25]/ ckeout1 54 [1] r4 [1] i/o p2[25] ? general purpose digital input/output pin. o ckeout1 ? sdram clock enable 1. p2[26]/ ckeout2/ mat3[0]/miso0 57 [1] t4 [1] i/o p2[26] ? general purpose digital input/output pin. o ckeout2 ? sdram clock enable 2. o mat3[0] ? match output for timer 3, channel 0. i/o miso0 ? master in slave out for ssp0. p2[27]/ ckeout3/ mat3[1]/mosi0 47 [1] p3 [1] i/o p2[27] ? general purpose digital input/output pin. o ckeout3 ? sdram clock enable 3. o mat3[1] ? match output for timer 3, channel 1. i/o mosi0 ? master out slave in for ssp0. p2[28]/ dqmout0 49 [1] p4 [1] i/o p2[28] ? general purpose digital input/output pin. o dqmout0 ? data mask 0 used with sdram and static devices. p2[29]/ dqmout1 43 [1] n3 [1] i/o p2[29] ? general purpose digital input/output pin. o dqmout1 ? data mask 1 used with sdram and static devices. p2[30]/ dqmout2/ mat3[2]/sda2 31 [1] l4 [1] i/o p2[30] ? general purpose digital input/output pin. o dqmout2 ? data mask 2 used with sdram and static devices. o mat3[2] ? match output for timer 3, channel 2. i/o sda2 ? i 2 c2 data input/output (this is not an open-drain pin). p2[31]/ dqmout3/ mat3[3]/scl2 39 [1] n2 [1] i/o p2[31] ? general purpose digital input/output pin. o dqmout3 ? data mask 3 used with sdram and static devices. o mat3[3] ? match output for timer 3, channel 3. i/o scl2 ? i 2 c2 clock input/output (this is not an open-drain pin). p3[0] to p3[31] i/o port 3: port 3 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. p3[0]/d0 197 [1] b4 [1] i/o p3[0] ? general purpose digital input/output pin. i/o d0 ? external memory data line 0. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 19 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p3[1]/d1 201 [1] b3 [1] i/o p3[1] ? general purpose digital input/output pin. i/o d1 ? external memory data line 1. p3[2]/d2 207 [1] b1 [1] i/o p3[2] ? general purpose digital input/output pin. i/o d2 ? external memory data line 2. p3[3]/d3 3 [1] e4 [1] i/o p3[3] ? general purpose digital input/output pin. i/o d3 ? external memory data line 3. p3[4]/d4 13 [1] f2 [1] i/o p3[4] ? general purpose digital input/output pin. i/o d4 ? external memory data line 4. p3[5]/d5 17 [1] g1 [1] i/o p3[5] ? general purpose digital input/output pin. i/o d5 ? external memory data line 5. p3[6]/d6 23 [1] j1 [1] i/o p3[6] ? general purpose digital input/output pin. i/o d6 ? external memory data line 6. p3[7]/d7 27 [1] l1 [1] i/o p3[7] ? general purpose digital input/output pin. i/o d7 ? external memory data line 7. p3[8]/d8 191 [1] d8 [1] i/o p3[8] ? general purpose digital input/output pin. i/o d8 ? external memory data line 8. p3[9]/d9 199 [1] c5 [1] i/o p3[9] ? general purpose digital input/output pin. i/o d9 ? external memory data line 9. p3[10]/d10 205 [1] b2 [1] i/o p3[10] ? general purpose digital input/output pin. i/o d10 ? external memory data line 10. p3[11]/d11 208 [1] d5 [1] i/o p3[11] ? general purpose digi tal input/output pin. i/o d11 ? external memory data line 11. p3[12]/d12 1 [1] d4 [1] i/o p3[12] ? general purpose digital input/output pin. i/o d12 ? external memory data line 12. p3[13]/d13 7 [1] c1 [1] i/o p3[13] ? general purpose digital input/output pin. i/o d13 ? external memory data line 13. p3[14]/d14 21 [1] h2 [1] i/o p3[14] ? general purpose digital input/output pin. i/o d14 ? external memory data line 14. on por, this pin serves as the boot0 pin. p3[15]/d15 28 [1] m1 [1] i/o p3[15] ? general purpose digital input/output pin. i/o d15 ? external memory data line 15. on por, this pin serves as the boot1 pin. boot[1:0] = 00 selects 8- bit external memory on cs1 . boot[1:0] = 01 is reserved. do not use. boot[1:0] = 10 selects 32 -bit external memory on cs1 . boot[1:0] = 11 selects 16 -bit external memory on cs1 . p3[16]/d16/ pwm0[1]/txd1 137 [1] f17 [1] i/o p3[16] ? general purpose digital input/output pin. i/o d16 ? external memory data line 16. o pwm0[1] ? pulse width modulator 0, output 1. o txd1 ? transmitter output for uart1. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 20 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p3[17]/d17/ pwm0[2]/rxd1 143 [1] f15 [1] i/o p3[17] ? general purpose digital input/output pin. i/o d17 ? external memory data line 17. o pwm0[2] ? pulse width modulator 0, output 2. i rxd1 ? receiver input for uart1. p3[18]/d18/ pwm0[3]/cts1 151 [1] c15 [1] i/o p3[18] ? general purpose digital input/output pin. i/o d18 ? external memory data line 18. o pwm0[3] ? pulse width modulator 0, output 3. i cts1 ? clear to send input for uart1. p3[19]/d19/ pwm0[4]/dcd1 161 [1] b14 [1] i/o p3[19] ? general purpose digital input/output pin. i/o d19 ? external memory data line 19. o pwm0[4] ? pulse width modulator 0, output 4. i dcd1 ? data carrier detect input for uart1. p3[20]/d20/ pwm0[5]/dsr1 167 [1] a13 [1] i/o p3[20] ? general purpose digital input/output pin. i/o d20 ? external memory data line 20. o pwm0[5] ? pulse width modulator 0, output 5. i dsr1 ? data set ready input for uart1. p3[21]/d21/ pwm0[6]/dtr1 175 [1] c10 [1] i/o p3[21] ? general purpose digital input/output pin. i/o d21 ? external memory data line 21. o pwm0[6] ? pulse width modulator 0, output 6. o dtr1 ? data terminal ready output for uart1. p3[22]/d22/ pcap0[0]/ri1 195 [1] c6 [1] i/o p3[22] ? general purpose digital input/output pin. i/o d22 ? external memory data line 22. i pcap0[0] ? capture input for pwm0, channel 0. i ri1 ? ring indicator input for uart1. p3[23]/d23/ cap0[0]/ pcap1[0] 65 [1] t6 [1] i/o p3[23] ? general purpose digital input/output pin. i/o d23 ? external memory data line 23. i cap0[0] ? capture input for timer 0, channel 0. i pcap1[0] ? capture input for pwm1, channel 0. p3[24]/d24/ cap0[1]/ pwm1[1] 58 [1] r5 [1] i/o p3[24] ? general purpose digital input/output pin. i/o d24 ? external memory data line 24. i cap0[1] ? capture input for timer 0, channel 1. o pwm1[1] ? pulse width modulator 1, output 1. p3[25]/d25/ mat0[0]/ pwm1[2] 56 [1] u2 [1] i/o p3[25] ? general purpose digital input/output pin. i/o d25 ? external memory data line 25. o mat0[0] ? match output for timer 0, channel 0. o pwm1[2] ? pulse width modulator 1, output 2. p3[26]/d26/ mat0[1]/ pwm1[3] 55 [1] t3 [1] i/o p3[26] ? general purpose digital input/output pin. i/o d26 ? external memory data line 26. o mat0[1] ? match output for timer 0, channel 1. o pwm1[3] ? pulse width modulator 1, output 3. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 21 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p3[27]/d27/ cap1[0]/ pwm1[4] 203 [1] a1 [1] i/o p3[27] ? general purpose digital input/output pin. i/o d27 ? external memory data line 27. i cap1[0] ? capture input for timer 1, channel 0. o pwm1[4] ? pulse width modulator 1, output 4. p3[28]/d28/ cap1[1]/ pwm1[5] 5 [1] d2 [1] i/o p3[28] ? general purpose digital input/output pin. i/o d28 ? external memory data line 28. i cap1[1] ? capture input for timer 1, channel 1. o pwm1[5] ? pulse width modulator 1, output 5. p3[29]/d29/ mat1[0]/ pwm1[6] 11 [1] f3 [1] i/o p3[29] ? general purpose digital input/output pin. i/o d29 ? external memory data line 29. o mat1[0] ? match output for timer 1, channel 0. o pwm1[6] ? pulse width modulator 1, output 6. p3[30]/d30/ mat1[1]/ rts1 19 [1] h3 [1] i/o p3[30] ? general purpose digital input/output pin. i/o d30 ? external memory data line 30. o mat1[1] ? match output for timer 1, channel 1. o rts1 ? request to send output for uart1. p3[31]/d31/ mat1[2] 25 [1] j3 [1] i/o p3[31] ? general purpose digital input/output pin. i/o d31 ? external memory data line 31. o mat1[2] ? match output for timer 1, channel 2. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. p4[0]/a0 75 [1] u9 [1] i/o p4[0] ? ]general purpose digital input/output pin. i/o a0 ? external memory address line 0. p4[1]/a1 79 [1] u10 [1] i/o p4[1] ? general purpose digital input/output pin. i/o a1 ? external memory address line 1. p4[2]/a2 83 [1] t11 [1] i/o p4[2] ? general purpose digital input/output pin. i/o a2 ? external memory address line 2. p4[3]/a3 97 [1] u16 [1] i/o p4[3] ? general purpose digital input/output pin. i/o a3 ? external memory address line 3. p4[4]/a4 103 [1] r15 [1] i/o p4[4] ? general purpose digital input/output pin. i/o a4 ? external memory address line 4. p4[5]/a5 107 [1] r16 [1] i/o p4[5] ? general purpose digital input/output pin. i/o a5 ? external memory address line 5. p4[6]/a6 113 [1] m14 [1] i/o p4[6] ? general purpose digital input/output pin. i/o a6 ? external memory address line 6. p4[7]/a7 121 [1] l16 [1] i/o p4[7] ? general purpose digital input/output pin. i/o a7 ? external memory address line 7. p4[8]/a8 127 [1] j17 [1] i/o p4[8] ? general purpose digital input/output pin. i/o a8 ? external memory address line 8. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 22 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p4[9]/a9 131 [1] h17 [1] i/o p4[9] ? general purpose digital input/output pin. i/o a9 ? external memory address line 9. p4[10]/a10 135 [1] g17 [1] i/o p4[10] ? general purpose digital input/output pin. i/o a10 ? external memory address line 10. p4[11]/a11 145 [1] f14 [1] i/o p4[11] ? general purpose digi tal input/output pin. i/o a11 ? external memory address line 11. p4[12]/a12 149 [1] c16 [1] i/o p4[12] ? general purpose digital input/output pin. i/o a12 ? external memory address line 12. p4[13]/a13 155 [1] b16 [1] i/o p4[13] ? general purpose digital input/output pin. i/o a13 ? external memory address line 13. p4[14]/a14 159 [1] b15 [1] i/o p4[14] ? general purpose digital input/output pin. i/o a14 ? external memory address line 14. p4[15]/a15 173 [1] a11 [1] i/o p4[15] ? general purpose digital input/output pin. i/o a15 ? external memory address line 15. p4[16]/a16 101 [1] u17 [1] i/o p4[16] ? general purpose digital input/output pin. i/o a16 ? external memory address line 16. p4[17]/a17 104 [1] p14 [1] i/o p4[17] ? general purpose digital input/output pin. i/o a17 ? external memory address line 17. p4[18]/a18 105 [1] p15 [1] i/o p4[18] ? general purpose digital input/output pin. i/o a18 ? external memory address line 18. p4[19]/a19 111 [1] p16 [1] i/o p4[19] ? general purpose digital input/output pin. i/o a19 ? external memory address line 19. p4[20]/a20/ sda2/sck1 109 [1] r17 [1] i/o p4[20] ? general purpose digital input/output pin. i/o a20 ? external memory address line 20. i/o sda2 ? i 2 c2 data input/output (this is not an open-drain pin). i/o sck1 ? serial clock for ssp1. p4[21]/a21/ scl2/ssel1 115 [1] m15 [1] i/o p4[21] ? general purpose digital input/output pin. i/o a21 ? external memory address line 21. i/o scl2 ? i 2 c2 clock input/output (this is not an open-drain pin). i/o ssel1 ? slave select for ssp1. p4[22]/a22/ txd2/miso1 123 [1] k14 [1] i/o p4[22] ? general purpose digital input/output pin. i/o a22 ? external memory address line 22. o txd2 ? transmitter output for uart2. i/o miso1 ? master in slave out for ssp1. p4[23]/a23/ rxd2/mosi1 129 [1] j15 [1] i/o p4[23] ? general purpose digital input/output pin. i/o a23 ? external memory address line 23. i rxd2 ? receiver input for uart2. i/o mosi1 ? master out slave in for ssp1. p4[24]/ oe 183 [1] b8 [1] i/o p4[24] ? general purpose digital input/output pin. o oe ? low active output enable signal. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 23 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller p4[25]/ we 179 [1] b9 [1] i/o p4[25] ? general purpose digital input/output pin. o we ? low active write enable signal. p4[26]/ bls0 119 [1] l15 [1] i/o p4[26] ? general purpose digital input/output pin. o bls0 ? low active byte lane select signal 0. p4[27]/ bls1 139 [1] g15 [1] i/o p4[27] ? general purpose digital input/output pin. o bls1 ? low active byte lane select signal 1. p4[28]/ bls2 / mat2[0]/txd3 170 [1] c11 [1] i/o p4 [28] ? general purpose digital input/output pin. o bls2 ? low active byte lane select signal 2. o mat2[0] ? match output for timer 2, channel 0. o txd3 ? transmitter output for uart3. p4[29]/ bls3 / mat2[1]/rxd3 176 [1] b10 [1] i/o p4[29] ? general purpose digital input/output pin. o bls3 ? low active byte lane select signal 3. o mat2[1] ? match output for timer 2, channel 1. i rxd3 ? receiver input for uart3. p4[30]/ cs0 187 [1] b7 [1] i/o p4[30] ? general purpose digital input/output pin. o cs0 ? low active chip select 0 signal. p4[31]/ cs1 193 [1] a4 [1] i/o p4[31] ? general purpose digital input/output pin. o cs1 ? low active chip select 1 signal. alarm 37 [8] n1 [8] o alarm ? rtc controlled output. this is a 1.8 v pin. it goes high when a rtc alarm is generated. usb_d ? 2 52 u1 i/o usb_d ? 2 ? usb port 2 bidirectional d ? line. dbgen 9 [1] f4 [1] i dbgen ? jtag interface control signal. also used for boundary scanning. tdo 2 [1] d3 [1] o tdo ? test data out for jtag interface. tdi 4 [1] c2 [1] i tdi ? test data in for jtag interface. tms 6 [1] e3 [1] i tms ? test mode select for jtag interface. trst 8 [1] d1 [1] i trst ? test reset for jtag interface. tck 10 [1] e2 [1] i tck ? test clock for jtag interface. th is clock must be slower than 1 ? 6 of the cpu clock (cclk) for t he jtag interface to operate. rtck 206 [1] c3 [1] i/o rtck ? jtag interface control signal. note: low on this pin while reset is low enables etm pins (p2[9:0]) to operate as trace port after reset. rstout 29 k3 o rstout ? this is a 3.3 v pin. low on this pin indicates LPC2420/2460 being in reset state. reset 35 [7] m2 [7] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at addres s 0. ttl with hysteresis, 5 v tolerant. xtal1 44 [8] m4 [8] i input to the oscillator circuit and internal clock generator circuits. xtal2 46 [8] n4 [8] o output from the oscillator amplifier. rtcx1 34 [8] k2 [8] i input to the rtc oscillator circuit. rtcx2 36 [8] l2 [8] o output from the rtc oscillator circuit. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 24 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [2] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input. when configured as a adc input, digital section of the pad is disabled. [3] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output function. when configured as the dac outp ut, digital section of the pad is disabled. [4] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus 400 khz specification. it requires an external pull-up to provide output functionality. when power is switc hed off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c-bus lines. open-drain configuration applies to al l functions on this pin. [5] pad provides digital i/o and usb functi ons. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). [6] 5 v tolerant pad with 5 ns glitch filter providing digital i/o functions with ttl le vels and hysteresis. [7] 5 v tolerant pad with 20 ns glitch filter providing digital i/o f unction with ttl leve ls and hysteresis. [8] pad provides special analog functionality. v ssio 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 [8] l3, t5, r9, p12, n16, h14, e15, a12, b6, a2 [8] i ground: 0 v reference for the digital i/o pins. v sscore 32, 84, 172 [8] k4, p10, d12 [8] i ground: 0 v reference for the core. v ssa 22 [8] j2 [8] i analog ground: 0 v reference. this should nominally be the same voltage as v ssio /v sscore , but should be isolated to minimize noise and error. v dd(3v3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 [8] g3, p6, p8, u13, p17, k16, c17, b13, c9, d7 [8] i 3.3 v supply voltage: this is the power supply voltage for the i/o ports. n.c. 30, 117, 141 [8] j4, l14, g14 [8] i not connected pins: these pins must be left unconnected (floating). v dd(dcdc)(3v3) 26, 86, 174 [8] h4, p11, d11 [8] i 3.3 v dc-to-dc converter supply voltage: this is the power supply for the on-chip dc-to-dc converter. v dda 20 [8] g4 [8] i analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. vref 24 [8] k1 [8] i adc reference: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. the level on this pin is used as a reference for adc and dac. vbat 38 [8] m3 [8] i rtc power supply: 3.3 v on this pin supplies the power to the rtc. table 4. pin description ?continued symbol pin ball type description
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 25 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7. functional description 7.1 architectural overview the LPC2420/2460 microcontroller consists of an arm7tdmi-s cpu with emulation support, the arm7 local bus for closely coup led, high-speed access to the majority of on-chip memory, the amba ahb interfacing to high-speed on-chip peripherals and external memory, and the amba apb for connection to other on-chip peripheral functions. the microcontroller permanently configures the arm7tdmi-s processor for little-endian byte order. the lpc2460 only implements two ahb in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vic, gp dma controller, and emc. the second ahb (lpc2460 only), referred to as ahb2, includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters wi th access to ahb2 are the arm7 and the ethernet block. ahb peripherals are allocated a 2 mb range of addresses at the very top of the 4 gb arm memory space. each ahb peripheral is allocated a 16 kb address space within the ahb address space. lo wer speed periph eral functions are conn ected to the apb. the ahb to apb bridge interfaces the apb to the ahb. apb periph erals are also allocated a 2 mb range of addresses, beginning at the 3.5 gb address point. each apb peripheral is allocated a 16 kb address space within the apb address space. the arm7tdmi-s processor is a general purp ose 32-bit microprocessor, which offers high performance and very low power consumpt ion. the arm architecture is based on reduced instruction set comput er (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? a 16-bit thumb set
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 26 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller the thumb set?s 16-bit instruction length allows it to approach higher density compared to standard arm code while retaining most of the arm?s performance. 7.2 on-chip sram the LPC2420/2460 includes a sram memory of 64 kb reserved for the arm processor exclusive use. this ram may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. a 16 kb sram block serving as a buffer for t he ethernet controller (lpc2460 only) and a 16 kb sram associated with the second ahb can be used both for data and code storage, too. the 2 kb rtc sram can be used for data storage only. the rtc sram is battery powered and retains the content in the absence of the main power supply. 7.3 memory map the LPC2420/2460 memory map incorporates several distinct regions as shown in ta b l e 5 and figure 4 . in addition, the cpu interrupt vectors may be remapped to allow them to reside in either boot rom or sram (see section 7.25.6 ). table 5. LPC2420/2460 memory usage and details address range general use address range details and description 0x0000 0000 to 0x3fff ffff fast i/o 0x3fff c000 to 0x3fff ffff fast gpio registers 0x4000 0000 to 0x7fff ffff on-chip ram 0x4000 0000 to 0x4000 ffff ram (64 kb) 0x7fe0 0000 to 0x7fe0 3fff ethernet ram (16 kb) (lpc2460 only) 0x7fd0 0000 to 0x7fd0 3fff usb ram (16 kb) 0x8000 0000 to 0xdfff ffff off-chip memory four static memory banks, 16 mb each 0x8000 0000 to 0x80ff ffff static memory bank 0 0x8100 0000 to 0x81ff ffff static memory bank 1 0x8200 0000 to 0x82ff ffff static memory bank 2 0x8300 0000 to 0x83ff ffff static memory bank 3 four dynamic memory banks, 256 mb each 0xa000 0000 to 0xafff ffff dynamic memory bank 0 0xb000 0000 to 0xbfff ffff dynamic memory bank 1 0xc000 0000 to 0xcfff ffff dynamic memory bank 2 0xd000 0000 to 0xdfff ffff dynamic memory bank 3 0xe000 0000 to 0xefff ffff apb peripherals 36 peripheral blocks, 16 kb each 0xf000 0000 to 0xffff ffff ahb peripherals
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 27 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.4 interrupt controller the arm processor core has two interrupt inputs called interrupt request (irq) and fast interrupt request (fiq). the vic takes 32 interrupt request inputs which can be programmed as fiq or vectored irq types. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiqs have the highest priority. if more than one request is assigned to fiq, the vic ors the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classified as fiq, because then the fiq fig 4. LPC2420/2460 memory map 0.0 gb 1.0 gb 0x0000 0000 reserved address space special registers on-chip static ram reserved address space 0x4000 0000 0x3fff 8000 0x3fff ffff 2.0 gb 0x8000 0000 0x7fff ffff boot rom 3.75 gb 4.0 gb 3.5 gb ahb peripherals apb peripherals 0xe000 0000 0xf000 0000 0xffff ffff 002aad316 external static and dynamic memory
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 28 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service ro utine can read a word from the vic that identifies which fiq source(s) is (are) requesting an interrupt. vectored irqs, which include all interrupt reques ts that are not classified as fiqs, have a programmable interrupt priority. when more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered vic channel will be serviced first. the vic ors the requests from all of the vectored irqs to produce the irq signal to the arm processor. the irq service routine can st art by reading a register from the vic and jumping to the address supplied by that register. 7.4.1 interrupt sources each peripheral device has one interrupt line connected to the vic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any pin on port 0 and port 2 (total of 64 pi ns) regardless of the se lected function, can be programmed to generate an in terrupt on a rising edge, a fa lling edge, or both. such interrupt request co ming from port 0 and/or po rt 2 will be combined with the eint3 interrupt requests. 7.5 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.6 external memory controller the LPC2420/2460 emc is an arm primece ll multiport memory controller peripheral offering support for a synchronous static memory devices such as ram, rom, and flash. in addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. the emc is an advanced microc ontroller bus architecture (amba) compliant peripheral. 7.6.1 features ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device suppor t including ram, rom, and flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce latency and to improve performance. ? 8/16/32 data and 24 address lines wide static memory support. ? 16 bit and 32 bit wide chip select sdram memory support. ? static memory features include:
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 29 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically co ntrol cke and clkout to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048, 4096, and 8192 row address synchronous memory parts. that is typical 512 mb, 256 mb, and 128 mb parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-r efresh through a chip reset if desired. note: synchronous static memory devices (synchronous burst mode) are not supported. 7.7 general purpose dma controller the gpdma is an amba ahb compliant peripheral allowing selected LPC2420/2460 peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. 7.7.1 features ? two dma channels. each channel can support a unidirectional transfer. ? the gpdma can transfer data between the 16 kb sram, external memory, and peripherals such as the sd/mmc, two ssps, and the i 2 s interface. ? single dma and burst dma request signals. each peripheral connected to the gpdma can assert either a burst dma request or a single dma request. the dma burst size is set by programming the gpdma. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma chan nel priority. each dma channel has a specific hardware priority. dma channel 0 has the highest priority and channel 1 has the lowest priority. if requests from two channels become active at the same time, the channel with the highest priority is serviced first. ? ahb slave dma programming interface. the gpdma is programmed by writing to the dma control registers over the ahb slave interface.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 30 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? one ahb master for transferring data. this interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. usually the burst size is set to half the size of the fifo in the peripheral. ? internal four-word fifo per channel. ? supports 8-bit, 16-bit, and 32-bit wide transactions. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? interrupt masking. the dma error and dma terminal count interrupt requests can be masked. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.8 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. LPC2420/2460 use accelerated gpio functions: ? gpio registers are relocated to the arm loca l bus so that the fa stest possible i/o timing can be achieved. ? mask registers allow treating sets of por t bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an analog input/outp ut can be programmed to generate an interrupt on a risi ng edge, a falling edge, or both. the edge detection is asynchro nous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake the chip up from power-down mode. 7.8.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? backward compatibility with ot her earlier devices is main tained with legacy port 0 and port 1 registers appea ring at the original addresses on the apb.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 31 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.9 ethernet (lpc2460 only) the ethernet block contains a full featured 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performa nce through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, cont rol frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share a dedicated ahb subsystem that is used to access the ethernet sram for ethernet data, control, and status information. all other ahb traffic in the LPC2420/2460 takes place on a different ahb subsystem, effectively separating ethernet activity from the rest of the system. the ethernet dma can also access off-chip memory via the emc, as well as the sram located on another ahb. however, using memory other than the ethernet sram, especi ally off-chip memory, will slow ethernet access to memory and increase the loading of its ahb. the ethernet block interfaces between an off-chip ethernet phy using the media independent interface (mii) or reduced m ii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. 7.9.1 features ? ethernet standards support: ? supports 10 mbit/s or 100 mbit/s phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3. ? fully compliant with 802.3x full duplex flow contro l and half duplex back pressure. ? flexible transmit and receive frame options. ? virtual local area network (vlan) frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and pre-fetching. ? enhanced ethernet features: ? receive filtering. ? multicast and broadcast frame support for both transmit and receive. ? optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. ? selectable automatic transmit frame padding. ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision back-off and frame retr ansmission. ? includes power management by clock switching.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 32 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip through standard mii or rmii interface. ? phy register access is available via the miim interface. 7.10 usb interface the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transactions are initiated by the host controller. the LPC2420/2460 usb interface includes a de vice, host, and otg co ntroller. details on typical usb interfacing solutions can be found in section 13.1 ? suggested usb interface solutions ? on page 64 7.10.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, endpoint buffer memory, and a dma controller. the serial interface engine dec odes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. when enabled, the dma controller transfers data between the endpoint buffer and the usb ram. 7.10.1.1 features ? fully compliant with usb 2.0 specification (full speed). ? supports 32 physical (16 logical) endpoints with a 4 kb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? supports softconnect and goodlink features. ? while usb is in the suspend mode, LPC2420/2460 can enter one of the reduced power modes and wake up on usb activity. ? supports dma transfers with the dma ram of 16 kb on all non-control endpoints. ? allows dynamic switching betwee n cpu-controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.10.2 usb host controller the host controller enables fu ll- and low-speed data exchange with usb devices attached to the bus. it consists of register interface, serial interface engine and dma controller. the register interface complies with the ohci specification.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 33 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.10.2.1 features ? ohci compliant. ? two downstream ports. ? supports per-port power switching. 7.10.3 usb otg controller usb otg is a supplement to the usb 2.0 specification that augments the capability of existing mobile devices and usb peripherals by adding host functiona lity for connection to usb peripherals. the otg controller integrates the host contro ller, device controller, and a master-only i 2 c-bus interface to implement otg dual-rol e device functionality. the dedicated i 2 c-bus interface controls an ex ternal otg transceiver. 7.10.3.1 features ? fully compliant with on-the-go supplement to the u sb 2.0 specification, revision 1.0a . ? hardware support for host negotiation protocol (hnp). ? includes a programmable timer required for hnp and session request protocol (srp). ? supports any otg transceiver compliant with the otg transceiver specification (cea-2011), rev. 1.0 . 7.11 can controller and accepta nce filters (lpc2460 only) the controller area network (can) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed ne tworks to low cost multiplex wiring. the can block is intended to support multip le can buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of can buses in industrial or automotive applications. each can controller has a regi ster structure sim ilar to the nxp sja1 000 and the pelican library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the arm environment. the main operational difference is that the recognition of received identifiers, known in can terminology as acceptance filtering, has been removed from the can controllers and centralized in a global acceptance filter. 7.11.1 features ? two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can specification 2.0b, iso 11898-1 . ? global acceptance filter recognizes 11-bit and 29-bit receive identifiers for all can buses.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 34 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. ? fullcan messages can gen erate interrupts. 7.12 10-bit adc the LPC2420/2460 contains one adc. it is a single 10-bit successive approximation adc with eight channels. 7.12.1 features ? 10-bit successive approximation adc ? input multiplexing among 8 pins ? power-down mode ? measurement range 0 v to v i(vref) ? 10-bit conversion time 2.44 s ? burst conversion mode for single or multiple inputs ? optional conversion on transition of input pin or timer match signal ? individual result registers for each adc channel to reduce interrupt overhead 7.13 10-bit dac the dac allows the LPC2420/2460 to generate a variable analog output. the maximum output value of the dac is v i(vref) . 7.13.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive 7.14 uarts the LPC2420/2460 contains four uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface. the uarts include a fractional baud rate generator. standard baud rates such as 115 200 bd can be achieved with any crystal frequency above 2 mhz. 7.14.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trig ger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 35 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware flow control (auto-cts/rts). ? uart3 includes an irda mode to support infrared communication. 7.15 spi serial i/o controller the LPC2420/2460 contains one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.15.1 features ? compliant with spi specification ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer 7.16 ssp serial i/o controller the LPC2420/2460 contains two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus . it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.16.1 features ? compatible with motorola spi , 4-wire ti ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? maximum spi bus data bit rate of one half (master mode) and one twelfth (slave mode) of the input clock rate ? dma transfers supported by gpdma 7.17 sd/mmc card interface the secure digital and multimed ia card interface (mci) allows access to external sd memory cards. the sd card interface conforms to the sd multimedia ca rd specification version 2.11 .
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 36 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.17.1 features ? the mci provides all functions specific to the sd/mmc memory card. these include the clock generation unit, power management control, and command and data transfer. ? conforms to multimedia card specification v2.11 . ? conforms to secure digital memory card phys ical layer specification, v0.96. ? can be used as a multimedia card bus or a secure digital memory card bus host. the sd/mmc can be connected to several multimedia cards or a single secure digital memory card. ? dma supported through the gpdma controller. 7.18 i 2 c-bus serial i/o controller the LPC2420/2460 contains three i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic contro l using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus and can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in LPC2420/2460 supports bit rates up to 400 kbit/s (fast i 2 c-bus). 7.18.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. ? i 2 c1 and i 2 c2 use standard i/o pins and do not support powering off of individual devices connected to the same bus lines. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. 7.19 i 2 s-bus serial i/o controllers the i 2 s-bus provides a standard communication interface for digital audio applications.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 37 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface on the LPC2420/2460 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.19.1 features ? the interface has separate input/output chan nels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 48 khz (16, 22.05, 32, 44.1, 48) khz. ? configurable word select period in master mode (separately for i 2 s-bus input and output). ? two 8 word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s-bus input and i 2 s-bus output. 7.20 general purpose 32-bit time rs/external event counters the LPC2420/2460 includes four 32-bit time r/counters. the timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. the timer/counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? up to four 32-bit capture channels per time r, that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 38 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? do nothing on match. 7.21 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on t he LPC2420/2460. the timer is designed to count cycles of the system derive d clock and optionally switch pins, generate interrupts or perform other actions when specified timer va lues occur, based on seven match registers. the pwm function is in addition to these fe atures and is based on match register events. the ability to separately contro l rising and falling edge locations allo ws the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. a dedicated match register controls the pwm c ycle rate, by resetting the count upon match. the other match register controls the pw m edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge contro lled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs. three match registers can be used to provid e a pwm output with both edges controlled. again, a dedicated match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additi onal double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the fa lling edge), and negative goi ng pwm pulses (when the falling edge occurs prior to the rising edge). 7.21.1 features ? LPC2420/2460 has two pwms with the same operational features. these may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. pwm0 acts as the master and pwm1 as the slave for this use. ? counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of bot h types. the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge co ntrolled pwm outputs can have either edge occur at any position within a cycle. this a llows for both positive going and negative going pulses.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 39 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and re petition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wit h pulse outputs to prevent generation of erroneous pulses. software must ?release? new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 7.22 watchdog timer the purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of time if it enters an erroneou s state. when enabl ed, the watchdog w ill generate a system reset if the user program fails to ?feed? (o r reload) the watchdog within a predetermined amount of time. 7.22.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 32 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the rtc clock, the internal rc oscillator (irc), or the apb peripheral clock. this gives a wide range of potential timing choices of watchdog o peration under different power reduction conditions. it also provides the ability to ru n the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for incr eased reliability. 7.23 rtc and battery ram the rtc is a set of counters for measuring ti me when system power is on, and optionally when it is off. it uses little power in power-down and deep power-down modes. on the LPC2420/2460, the rtc can be clocked by a separate 32.768 khz oscillator or by a programmable prescale divider based on the apb clock. also, the rtc is powered by its own power supply pin, vbat, which can be connected to a battery or to the same 3.3 v supply used by the rest of the device.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 40 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, whic h can be supplied by an external battery. when the cpu and the rest of chip functi ons are stopped and power removed, the rtc can supply an alarm output that can be used by external hardware to restore chip power and resume operation. 7.23.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated 32 khz oscillator or programmabl e prescaler from apb clock. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? an alarm output pin is included to assist in waking up when the chip has had power removed to all functions except the rtc and battery ram. ? periodic interrupts can be generated from in crements of any field of the time registers, and selected fractional second values. this enhancement enables the rtc to be used as a system timer. ? 2 kb data sram powered by vbat. ? rtc and battery ram power supply is isolated from the rest of the chip. 7.24 clocking and power control 7.24.1 crystal oscillators the LPC2420/2460 includes thre e independent oscillators. thes e are the main oscillator, the internal rc oscillator, and the rtc oscilla tor. each oscillator ca n be used for more than one purpose as required in a particular application. any of the three clock sources can be chosen by software to drive the pll and ultimately the cpu. following reset, the LPC2420/ 2460 will operate from the in ternal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency. 7.24.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 4 mhz. the irc is trimmed to 1 % accuracy. upon power-up or any chip reset, the LPC2420/2460 uses the irc as the clock source. software may later switch to one of the other available clock sources. 7.24.1.2 main oscillator the main oscillator can be used as the clock so urce for the cpu, with or without using the pll. the main oscillator ope rates at frequencies of 1 mhz to 24 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the pll. the clock selected as the pll inpu t is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 41 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.24.2 for additional information. 7.24.1.3 rtc oscillator the rtc oscillator can be used as the clock so urce for the rtc and/or the wdt. also, the rtc oscillator can be used to drive the pll and the cpu. 7.24.2 pll the pll accepts an input clock frequency in the range of 32 khz to 24 mhz. the input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the cpu and the usb block. the pll input, in the range of 32 khz to 24 mhz, may initially be divided down by a value ?n?, which may be in the range of 1 to 256. this input divi sion provides a wide range of output frequencies from the same input frequency. following the pll input divider is the pll mult iplier. this can multiply the input divider output through th e use of a current controlled oscilla tor (cco) by a value ?m?, in the range of 1 through 32768. the resulting frequency must be in the range of 275 mhz to 550 mhz. the multiplier works by dividing the cco output by the value of m, then using a phase-frequency detector to compare the divided cco output to the multiplier input. the error value is used to adjust the cco frequency. the pll is turned off and bypassed following a chip reset and by entering power-down mode. pll is enabled by software only. the pr ogram must configure and activate the pll, wait for the pll to lock, then conn ect to the pll as a clock source. 7.24.3 wake-up timer the LPC2420/2460 begins operation at powe r-up and when awakened from power-down and deep-power down modes by using the 4 mhz irc oscillator as th e clock source. this allows chip operation to resume quickly. if th e main oscillator or th e pll is needed by the application, software will need to enable these features an d wait for them to stabilize before they are used as a clock source. when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other function s are turned off during powe r-down and deep power-down modes, any wake-up of the processor from power-down modes makes use of the wake-up timer. the wake-up timer mo nitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to the chip, or when some event caused the chip to exit power-down mode, some time is required for the oscilla tor to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the ch aracteristics of the oscillator it self under the existing ambient conditions.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 42 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.24.4 power control the LPC2420/2460 supports a variety of power control features. there are four special modes of processor power reduction: idle mode, sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power ve rsus processing speed based on application requirements. in addition, peripheral power co ntrol allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are no t required for the application. each of the peripherals has its own clock divider wh ich provides even better power control. the LPC2420/2460 also implements a separate power domain in order to allow turning off power to the bulk of the device while mainta ining operation of the rtc and a small sram, referred to as the battery ram. 7.24.4.1 idle mode in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.24.4.2 sleep mode in sleep mode, the oscillator is shut down an d the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout sleep mode and the logic levels of chip pins remain static. the output of the irc is disabled but the irc is not powered down for a fast wake-up later. the 32 khz rtc oscillator is not stopped because the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the cclk and usb clock dividers automati cally get reset to zero. the sleep mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, sleep mode reduces chip power consumption to a very low value. on the wake-up from sleep mode, if the irc was used before entering sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. if the main external oscillator was used, the code exec ution will resume when 4096 cycles expire. the customers need to reconfigure the pll and clock dividers accordingly. 7.24.4.3 power-down mode power-down mode does everyt hing that sleep mode does but also turns off the irc oscillator. on the wake-up from power-down mode, if the irc was used before entering power-down mode, it will take irc 60 s to start-up. after this 4 irc cycles will expire before the code execution can then be resumed if the code was running from sram. the customers need to reconfigure the pll and clock dividers accordingly after a wake-up from power-down mode.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 43 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.24.4.4 deep power-down mode deep power-down mode is similar to the power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. this produces the lowest possible power consum ption without removing power from the entire chip. since the deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full chip reset. if power is supplied to the LPC2420/2460 during deep power-down mode, wake-up can be caused by the rtc alarm interrupt or by external reset. while in deep power-down mode, external device power may be removed. in this case, the LPC2420/2460 will start up when external power is restored. essential data may be retained through deep power-down mode (or through complete powering off of the chip) by storing data in t he battery ram, as long as the external power to the vbat pin is maintained. 7.24.4.5 power domains the LPC2420/2460 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the battery ram. on the LPC2420/2460, i/o pads are powered by the 3.3 v (v dd(3v3) ) pins, while the v dd(dcdc)(3v3) pins power the on-chip dc-to-dc converter which in turn provides power to the cpu and most of the peripherals. although both the i/o pad ring and the core require a 3.3 v supply, different powering schemes can be used depending on th e actual application requirements. the first option assumes that power consumptio n is not a concern and the design ties the v dd(3v3) and v dd(dcdc)(3v3) pins together. this approach requires only one 3.3 v power supply for both pads, the cpu, and peripherals. while this solution is simple, it does not support powering down the i/o pad ring ?on the fly? while keeping the cpu and peripherals alive. the second option uses tw o power supplies; a 3.3 v supply for the i/o pads (v dd(3v3) ) and a dedicated 3.3 v supply for the cpu (v dd(dcdc)(3v3) ). having the on-chip dc-dc converter powered independently from the i/o pad ring enables shutting down of the i/o pad power supply ?on the fly?, while the cpu and peripherals stay active. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, whic h can be supplied by an external battery. when the cpu and the rest of chip functi ons are stopped and power removed, the rtc can supply an alarm output that may be used by external hardware to restore chip power and resume operation.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 44 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.25 system control 7.25.1 reset reset has four sources on the LPC2420/2460: the reset pin, the watchdog reset, power-on reset, and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 7.24.3 ? wake-up timer ? ), causing reset to remain asserted until the external reset is de-asserted, the oscillator is running, and a fixe d number of clocks have passed. once the internal reset is removed, all of the processor and peripheral registers have been initialized to predetermined values and the LPC2420/2460 continues with booting from an external static memory. 7.25.2 boot process the processor always boots from the off-chip static memory bank 1, executing code from address 0x8100 0000 (see table 5 ? LPC2420/2460 memory usage and details ? ). during the boot process initiated by por, the boot pins p3[15]/d15 and p3[14]/d14 are sampled, and the external memory banks 0 and 1 are configured with the same data bus width. the data bus width is determined by the setting of the two boot pins. unused address pins are configured as gpio. see section 13.4 ? suggested boot memory interface solutions ? for an example of address and data bus interfacing. remark: after por, the address ranges of chip se lect 1 and chip select 0 are swapped. the user code residing in the external boot memory must be linked to execute from address location 0x8000 0000. when booting from external memory, the interrupt vectors are mapped to the bottom of the external memory. once booting is over, the application must map interrupt vectors to the proper domain. 7.25.3 brownout detection the LPC2420/2460 includes 2-stage monitoring of the voltage on the v dd(dcdc)(3v3) pins. if this voltage falls below 2.95 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt in the interrupt enable register in the vic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection asserts a bod reset and generates a reset (if this reset source is enabled in software) to inactivate the LPC2420/2460 when the voltage on the v dd(dcdc)(3v3) pins falls below 2.65 v. the bod circuit main tains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.95 v and 2.65 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.95 v detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 45 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 7.25.4 ahb the lpc2460 implements two ahb in order to a llow the ethernet block to operate without interference caused by other system activity . the primary ahb, referred to as ahb1, is implemented on LPC2420 as well and includes the vectored interrupt controller, gpdma controller, usb interface, and 16 kb sram. the second ahb, referred to as ahb2, is implemented on lpc2460 only and includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the usb block, the gpdma function, and the etherne t block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. 7.25.5 external interrupt inputs the LPC2420/2460 includes up to 68 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 7.25.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. vectors may be mapped to the bottom of the boot rom, the sram, or external memory. this allows code running in different memory spaces to have control of the interrupts. 7.26 emulation and debugging the LPC2420/2460 support emulation and debu gging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on p2[0] to p2[9]. this means that all communication, timer, and interface peripherals residing on other pins are av ailable during the development and debugging phase as they are when the application is run in the embedded system itself. 7.26.1 embeddedice the embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. the embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm7tdmi-s core present on the target system. the arm core has a debug co mmunication channel (dcc) fu nction built-in. the dcc allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. the dcc is accessed as a coprocessor 14 by t he program running on the arm7tdmi-s core. the dcc allows the jtag port to be used for sending and receiving data without affecting the normal program flow. the dcc data and control registers are mapped in to addresses in the embeddedice logic.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 46 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller the jtag clock (tck) must be slower than 1 ? 6 of the cpu clock (cclk) for the jtag interface to operate. 7.26.2 embedded trace since the LPC2420/2460 have significant amounts of on-chip memories, it is not possible to determine how the processor core is oper ating simply by observing the external pins. the etm provides real-time trace capabilit y for deeply embedded processor cores. it outputs information about proces sor execution to a trace port. a software debugger allows configuration of the etm using a jtag interf ace and displays the tr ace information that has been captured. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer captures the trace information under software debugger control. the trace port can broadcast the instruction trace in formation. instruction trace (or pc trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is significan tly compressed by only broadcasting branch addresses as well as a set of status signals th at indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 7.26.3 realmonitor realmonitor is a configurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communi cates with the host using the dcc, which is present in the embeddedice logic. the lpc24 20/2460 contain a specif ic configuration of realmonitor software programmed into the on-chip rom memory.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 47 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ssio /v sscore unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k series resistor. table 6. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.6 v v dda analog 3.3 v pad supply voltage ? 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc ? 0.5 +4.6 v v i(vref) input voltage on pin vref ? 0.5 +4.6 v v ia analog input voltage on adc related pins ? 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(3v3) supply voltage is present [2] ? 0.5 +6.0 v other i/o pins [2] [3] ? 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma t stg storage temperature [5] ? 65 +150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [6] ? 2 500 +2 500 v
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 48 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 9. static characteristics table 7. static characteristics t amb = ? 40 c to +85 c for commercial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.3 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat [2] 2.0 3.3 3.6 v v i(vref) input voltage on pin vref 2.5 3.3 v dda v i dd(dcdc)act(3v3) active mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb = 25 c; code while(1){} executed from the on-chip sram; no peripherals enabled; pclk = cclk / 8 cclk = 12 mhz - 17.4 - ma cclk = 72 mhz - 66.1 - ma i dd(dcdc)pd(3v3) power-down mode dc-to-dc converter supply current (3.3 v) [3] - 113 - a i dd(dcdc)dpd(3v3) deep power-down mode dc-to-dc converter supply current (3.3 v) [3] - 20 - a i batact active mode battery supply current [4] - 20 - a i bat battery supply current deep power-down mode [3] - 20 - a standard port pins, reset , rtck i il low-level input current v i = 0 v; no pull-up - - 3 a i ih high-level input current v i = v dd(3v3) ; no pull-down - - 3 a i oz off-state output current v o = 0 v; v o = v dd(3v3) ; no pull-up/down - - 3 a i latch i/o latch-up current ? (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 c - - 100 ma v i input voltage pin configured to provide a digital function [5] [6] [7] [8] 0 - 5.5 v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 49 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma [9] v dd(3v3) ? 0.4 - - v v ol low-level output voltage i ol = ? 4 ma [9] - - 0.4 v i oh high-level output current v oh = v dd(3v3) ? 0.4 v [9] ? 4 - - ma i ol low-level output current v ol = 0.4 v [9] 4 - - ma i ohs high-level short-circuit output current v oh = 0 v [10] - - ? 45 ma i ols low-level short-circuit output current v ol = v dda [10] - - 50 ma i pd pull-down current v i = 5 v [11] 10 50 150 a i pu pull-up current v i = 0 v ? 15 ? 50 ? 85 a v dd(3v3) < v i < 5 v [11] 0 0 0 a i 2 c-bus pins (p0[27] and p0[28]) v ih high-level input voltage 0.7v dd(3v3) - - v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.5v dd(3v3) - v v ol low-level output voltage i ols = 3 ma [9] - - 0.4 v i li input leakage current v i = v dd(3v3) [12] - 2 4 a v i = 5 v - 10 22 a oscillator pins v i(xtal1) input voltage on pin xtal1 ? 0.5 1.8 1.95 v v o(xtal2) output voltage on pin xtal2 ? 0.5 1.8 1.95 v v i(rtcx1) input voltage on pin rtcx1 ? 0.5 1.8 1.95 v v o(rtcx2) output voltage on pin rtcx2 ? 0.5 1.8 1.95 v table 7. static characteristics ?continued t amb = ? 40 c to +85 c for commercial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 50 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages [2] the rtc typically fails when v i(vbat) drops below 1.6 v. [3] v dd(dcdc)(3v3) = 3.3 v; v dd(3v3) = 3.3 v; v i(vbat) = 3.3 v; t amb = 25 c. [4] on pin vbat. [5] including voltage on outputs in 3-state mode. [6] v dd(3v3) supply voltages must be present. [7] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [8] please also see the errata note in errata sheet. [9] accounts for 100 mv voltage drop in all supply lines. [10] allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [12] to v ssio /v sscore . [13] includes external resistors of 33 1 % on d+ and d ? . usb pins i oz off-state output current 0 v < v i < 3.3 v - - 10 a v bus bus supply voltage - - 5.25 v v di differential input sensitivity voltage | (d+) ? (d ? ) | 0.2 - - v v cm differential common mode voltage range includes v di range 0.8 - 2.5 v v th(rs)se single-ended receiver switching threshold voltage 0.8 - 2.0 v v ol low-level output voltage for low-/full-speed r l of 1.5 k to 3.6 v - - 0.18 v v oh high-level output voltage (driven) for low-/full-speed r l of 15 k to gnd 2.8 - 3.5 v c trans transceiver capacitance pin to gnd - - 20 pf z drv driver output impedance for driver which is not high-speed capable with 33 series resistor; steady state drive [13] 36 - 44.1 r pu pull-up resistance softconnect = on 1.1 - 1.9 k table 7. static characteristics ?continued t amb = ? 40 c to +85 c for commercial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 51 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 9.1 power-down mode v i(vbat) = v dd(dcdc)(3v3) = 3.3 v; t amb = 25 c. fig 5. i/o maximum supply current i dd(io) versus temperature in power-down mode v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb = 25 c. fig 6. rtc battery maximum supply current i bat versus temperature in power-down mode 002aae049 ? 2 2 0 4 i dd(io) ( a) ? 4 temperature ( c) ? 40 85 35 10 60 ? 15 v dd(3v3) = 3.3 v v dd(3v3) = 3.0 v 002aae050 v i(vbat) = 3.3 v v i(vbat) = 3.0 v 10 30 20 40 i bat ( a) 0 temperature ( c) ? 40 85 35 10 60 ? 15
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 52 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 9.2 deep power-down mode v dd(3v3) = v i(vbat) = 3.3 v; t amb = 25 c. fig 7. total dc-to-dc converter supply current i dd(dcdc)pd(3v3) at different temperatures in power-down mode 002aae051 200 600 400 800 0 temperature ( c) ? 40 85 35 10 60 ? 15 v dd(dcdc)(3v3) = 3.3 v v dd(dcdc)(3v3) = 3.0 v i dd(dcdc)pd(3v3) ( a) v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb = 25 c. fig 8. i/o maximum supply current i dd(io) versus temperature in deep power-down mode temperature ( c) ? 40 85 35 10 60 ? 15 002aae046 100 200 300 i dd(io) ( a) 0 v dd(3v3) = 3.3 v v dd(3v3) = 3.0 v
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 53 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller v dd(3v3) = v dd(dcdc)(3v3) = 3.3 v; t amb = 25 c fig 9. rtc battery maximum supply current i bat versus temperature in deep power-down mode v dd(3v3) = v i(vbat) = 3.3 v; t amb = 25 c. fig 10. total dc-to-dc converter maximum supply current i dd(dcdc)dpd(3v3) versus temperature in deep power-down mode 002aae047 10 30 20 40 i bat ( a) 0 temperature ( c) ? 40 85 35 10 60 ? 15 v i(vbat) = 3.3 v v i(vbat) = 3.0 v 002aae048 temperature ( c) ? 40 85 35 10 60 ? 15 i dd(dcdc)dpd(3v3) ( a) 40 80 20 60 100 0 v dd(dcdc)(3v3) = 3.3 v v dd(dcdc)(3v3) = 3.0 v
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 54 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 10. dynamic characteristics [1] characterized but not implemented as production test. guaranteed by design. [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. table 8. dynamic characteristics of usb pins (full-speed) c l = 50 pf; r pu = 1.5 k on d+ to v dd(3v3) ,unless otherwise specified. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r / t f - - 109 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 12 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 12 ? 2 - +5 ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9 - +9 ns t eopr1 eop width at receiver must reject as eop; see figure 12 [1] 40 - - ns t eopr2 eop width at receiver must accept as eop; see figure 12 [1] 82 - - ns table 9. dynamic characteristics t amb = ? 40 c to +85 c for commercial applications; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 1 - 24 mhz t cy(clk) clock cycle time 42 - 1000 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns i 2 c-bus pins (p0[27] and p0[28]) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] - - ns ssp interface t su(spi_miso) spi_miso set-up time t amb = 25 c; measured in spi master mode; see figure 13 - 11 - ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 55 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-bit microcontroller table 10. dynamic characteristics: static external memory interface c l = 30 pf, t amb = ? 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit common to read and write cycles [1] t cslav cs low to address valid time ? 0.29 0.20 2.54 ns read cycle parameters [1] [2] t oelav oe low to address valid time ? 0.29 0.20 2.54 ns t csloel cs low to oe low time ? 0.78 + t cy(cclk) waitoen 0 + t cy(cclk) waitoen 0.49 + t cy(cclk) waitoen ns t am memory access time [3] [4] (waitrd ? waitoen + 1) t cy(cclk) ? 8.11 (waitrd ? waitoen + 1) t cy(cclk) ? 9.57 (waitrd ? waitoen + 1) t cy(cclk) ? 12.70 ns t h(d) data input hold time [5] 1.29 4.22 5.20 ns t cshoeh cs high to oe high time ? 0.49 0 0.20 ns t oehanv oe high to address invalid time ? 0.20 0.20 2.44 ns t oeloeh oe low to oe high time ? 0.59 + (waitrd ? waitoen + 1) t cy(cclk) 0 + (waitrd ? waitoen + 1) t cy(cclk) 0.10 + (waitrd ? waitoen + 1) t cy(cclk) t blslav bls low to address valid time ? 0.39 0 2.54 ns t cshblsh cs high to bls high time ? 0.88 0.49 0.68 ns write cycle parameters [1] [6] t cslwel cs low to we low time ? 0.88 + t cy(cclk) (1 + waitwen) 0.10 + t cy(cclk) (1 + waitwen) 0.20 + t cy(cclk) (1 + waitwen) ns t cslblsl cs low to bls low time ? 0.88 0.49 0.98 ns t weldv we low to data valid time 0.68 2.54 5.86 ns t csldv cs low to data valid time 0 2.64 4.79 ns t welweh we low to we high time [3] ? 0.78 + t cy(cclk) (waitwr ? waitwen + 1) 0 + t cy(cclk) (waitwr ? waitwen + 1) 0.10 + t cy(cclk) (waitwr ? waitwen + 1) ns t blslblsh bls low to bls high time [3] ? 0.88 + t cy(cclk) (waitwr ? waitwen + 3) 0 + t cy(cclk) (waitwr ? waitwen + 3) 0.59 + t cy(cclk) (waitwr ? waitwen + 3) ns t wehanv we high to address invalid time [3] 0 + t cy(cclk) 0.20 + t cy(cclk) 2.74 + t cy(cclk) ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 56 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-bit microcontroller [1] v oh = 2.5 v, v ol = 0.2 v. [2] v ih = 2.5 v, v il = 0.5 v. [3] t cy(cclk) = 1 ? cclk . [4] latest of address valid, cs low, oe low to data valid. [5] earliest of cs high, oe high, address change to data invalid. [6] byte lane state bit (pb) = 1. t wehdnv we high to data invalid time [3] 0.78 2.54 5.96 ns t blshanv bls high to address invalid time [3] ? 0.29 0.20 2.54 ns t blshdnv bls high to data invalid time [3] 0 2.54 5.37 ns table 10. dynamic characteristics: static external memory interface ?continued c l = 30 pf, t amb = ? 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 57 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller table 11. dynamic characteristics: dynamic external memory interface c l = 30 pf, t amb = ? 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit common t d(sv) chip select valid delay time - 1.05 1.76 ns t h(s) chip select hold time 0.1 1.02 - ns t d(rasv) row address strobe valid delay time - 1.51 1.95 ns t h(ras) row address strobe hold time 0.5 1.51 - ns t d(casv) column address strobe valid delay time - 0.98 1.27 ns t h(cas) column address strobe hold time 0.1 0.97 - ns t d(wv) write valid delay time - 0.84 1.95 ns t h(w) write hold time 0.1 0.84 - ns t d(gv) output enable valid delay time - 0.95 1.86 ns t h(g) output enable hold time 0.1 1 - ns t d(av) address valid delay time - 0.87 1.95 ns t h(a) address hold time 0.1 0.81 - ns read cycle parameters t su(d) data input set-up time 0.51 2.24 - ns t h(d) data input hold time 0.57 2.41 - ns write cycle parameters t d(qv) data output valid delay time - 2.65 4.36 ns t h(q) data output hold time 0.49 2.61 - ns
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 58 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 10.1 timing fig 11. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa90 7 fig 12. differential data-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop fig 13. miso line set-up time in ssp master mode t su(spi_miso) sck shifting edges mosi miso 002aad32 6 sampling edges
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 59 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 14. external memory read access cs addr data oe bls t cslav t oelav t oeloeh t csloel t am t h(d) t cshoeh t oehanv 002aad95 5 t blslav t cshblsh fig 15. external memory write access addr data bls/we oe t cslwel t cslblsl t weldv t csldv t welweh t blslblsh t wehanv t blshanv t wehdnv t blshdnv 002aad95 6 t avcsl cs
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 60 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 16. signal timing 002aad6 36 reference clock output signal (o) input signal (i) t d(xxx) t h(xxx) t h(d) t su(d)
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 61 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 11. adc electrical characteristics [1] conditions: v ssa = 0 v, v dda = 3.3 v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 17 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 17 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 17 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 17 . [7] the absolute error (e t ) is the maximum difference between the center of the st eps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 17 . [8] see figure 18 . table 12. adc characteristics v dda = 2.5 v to 3.6 v; t amb = ? 40 c to +85 c unless otherwise specified; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] - - 1 lsb e l(adj) integral non-linearity [1] [4] - - 2 lsb e o offset error [1] [5] - - 3 lsb e g gain error [1] [6] - - 0.5 % e t absolute error [1] [7] - - 4 lsb r vsi voltage source interface resistance [8] - - 40 k
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 62 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 17. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 63 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 18. suggested adc interface - LPC2420/2460 ad0[y] pin lpc2xxx ad0[y] sample ad0[y] 20 k 3 pf 5 pf r vsi v ssio, v sscore v ext 002aad58 6
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 64 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 12. dac electrical characteristics 13. application information 13.1 suggested usb interface solutions table 13. dac electrical characteristics v dda = 2.7 v to 3.6 v; t amb = ? 40 c to +85 c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error - 1 - lsb e l(adj) integral non-linearity - 1.5 - lsb e o offset error - 0.6 - % e g gain error - 0.6 - % c l load capacitance - 200 - pf r l load resistance 1 - - k fig 19. LPC2420/2460 usb interface on a self-powered device lpc24xx usb-b connector usb_d+ usb_connect soft-connect switch usb_d ? v bus v ssio, v sscore v dd(3v3) r1 1.5 k r s = 33 002aad587 r s = 33 usb_up_led
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 65 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 20. LPC2420/2460 usb interface on a bus-powered device lpc24xx v dd(3v3) r1 1.5 k r2 usb_up_led 002aad588 usb-b connector usb_d+ usb_d ? v bus v ssio, v sscore r s = 33 r s = 33
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 66 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 21. LPC2420/2460 usb otg port configuration: us b port 1 otg dual-role device, usb port 2 host usb_up_led1 usb_d+1 usb_d ? 1 usb_pwrd2 usb_sda1 usb_scl1 rstout 15 k 15 k lpc24xx usb-a connector mini-ab connector 33 33 33 33 v dd v dd v dd usb_up_led2 v dd usb_ovrcr2 lm3526-l ena in 5 v outa flaga v dd d+ d ? v bus usb_ppwr2 usb_d+2 usb_d ? 2 002aad58 9 r7 r4 r5 r6 r1 r2 r3 r4 r8 usb_int1 reset_n adr/psw speed suspend oe_n/int_n scl sda int_n v bus id dp dm isp1302 v ssio, v sscore v ssio, v sscore
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 67 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 22. LPC2420/2460 usb otg port configuration: vp_vm mode usb_tx_dp1 usb_tx_dm1 usb_rcv1 usb_rx_dp1 usb_rx_dm1 usb_scl1 usb_sda1 speed adr/psw sda scl reset_n int_n vp vm suspend oe_n/int_n se0_vm dat_vp rcv v bus id dp dm lpc24xx isp1302 usb mini-ab connector 33 33 002aad590 usb_tx_e1 rstout v dd v dd usb_int1 usb_up_led1 v dd v ssio, v sscore
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 68 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 23. LPC2420/2460 usb otg port configurat ion: usb port 2 device, usb port 1 host usb_up_led1 usb_d+1 usb_d ? 1 usb_pwrd1 15 k 15 k lpc24xx usb-a connector usb-b connector 33 33 33 33 002aad595 v dd usb_up_led2 usb_connect2 v dd v dd usb_ovrcr1 usb_ppwr1 lm3526-l ena in 5 v flaga outa v dd d+ d ? d+ d ? v bus usb_d+2 usb_d ? 2 v bus v bus v ssio, v sscore v ssio, v sscore
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 69 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 13.2 xtal1 input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv rms is needed. for more details see the lpc24xx user manual um10237 . fig 24. LPC2420/2460 usb otg port configuration: usb port 1 host, usb port 2 host usb_up_led1 usb_d+1 usb_d ? 1 usb_pwrd1 usb_pwrd2 15 k 15 k 15 k 15 k lpc24xx usb-a connector usb-a connector 33 33 33 33 002aad596 v dd usb_up_led2 v dd usb_ovrcr1 usb_ovrcr2 usb_ppwr1 lm3526-l ena enb in 5 v flaga outa outb flagb v dd v dd d+ d ? d+ d ? v bus v bus usb_ppwr2 usb_d+2 usb_d ? 2 v ssio, v sscore v ssio, v sscore
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 70 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 13.3 xtal and rtc printed circuit board (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 and c x2 , and c x3 in case of third overtone crystal usage, have a common ground plane. the external components must also be connected to the grou nd plain. loops must be made as small as possible, in order to keep the noise couple d in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 13.4 suggested boot memory interface solutions ?a_m? and ?a_b? in the following figures refer to the highest order address line of the memory chip and the highest order microcontroller?s address line used respectively. fig 25. slave mode operation of the on-chip oscillator lpc2xxx xtal1 c i 100 pf c g 002aae71 8 fig 26. booting from two 8-bit memory chips 002aad32 2 ce oe we io[7:0] a[a_m:0] cs1 oe bls1 d[15:8] a[a_b:1] ce oe we io[7:0] a[a_m:0] bls0 d[7:0] 8-bit memory 8-bit memory
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 71 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 27. booting from a single 16-bit memory chip 002aad32 3 ce oe we io[15:0] a[a_m:0] we ub lb cs1 oe d[15:0] a[a_b:1] bls1 bls0 16-bit memory
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 72 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 14. package outline fig 28. package outline sot459-1 (lqfp208) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.15 29.85 1.43 1.08 7 0 o o 0.08 0.12 1 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot459-1 136e30 ms-026 00-02-06 03-02-20 d (1) 28.1 27.9 h d 30.15 29.85 e z 1.43 1.08 d pin 1 index b p e e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale lqfp208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm sot459 -1 a max. 1.6
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 73 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller fig 29. package outline sot950-1 (tfbga208) references outline version european projection issue date iec jedec jeita sot950-1 - - - sot950- 1 06-06-01 06-06-14 unit a max mm 1.2 0.4 0.3 0.8 0.6 15.1 14.9 15.1 14.9 0.8 12.8 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) t fbga208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 12.8 v w y 0.12 y 1 c y c y 1 x b ball a1 index area e 2 e 1 e e a c b ? v m c ? w m a b c d e f h k g l j m n p r u t 246810121416 1 3 5 7 9 11 13 15 17 ball a1 index area b a d e detail x a a 2 a 1
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 74 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 15. abbreviations table 14. acronym list acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dcc debug communication channel dma direct memory access eop end of packet etm embedded trace macrocell gp general purpose gpio general purpose input/output irda infrared data association iap in-application programming isp in-system programming jtag joint test action group mii media independent interface miim media independent interface management ohci open host controller interface otg on-the-go phy physical layer pll phase-locked loop por power-on reset pwm pulse width modulator rmii reduced media independent interface sd/mmc secure digital/multimediacard se0 single ended zero spi serial peripheral interface ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 75 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 16. revision history table 15. revision history document id release date data sheet status change notice supersedes LPC2420_60_5 20100224 preliminary data sheet - LPC2420_60_4 modifications: ? table 7 : merged power-down mode information into one table. ? table 7 : changed typical values from 19 to 20 for i dd(dcdc)dpd(3v3) , i batact , and i bat . ? added table 13 ? dac electrical characteristics ? . LPC2420_60_4 20091015 preliminary data sheet - LPC2420_60_3 modifications: ? added LPC2420fet208. ? added deep power-down mode information. ? table 6: changed esd min/max to ? 2500/+2500. ? table 7: updated conditions and typical values for i dd(dcdc)act(3v3) . ? table 7: updated table note 13. ? table 7: updated min, typical and max values for oscillator pins. ? added section 13.2 ?xtal1 input?. ? added section 13.3 ?xtal and rtc printed circuit board (pcb) layout guidelines?. ? figure 21: changed isp1301 to isp1302. ? figure 22: changed isp1301 to isp1302. ? section 7.25.3 ?brownout detection?: changed v dd(3v3) to v dd(dcdc)(3v3) . LPC2420_60_3 20081120 preliminary data sheet - lpc2460_2 lpc2460_2 20080201 preliminary data sheet - lpc2460_1 lpc2460_1 20080123 preliminary data sheet - -
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 76 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless the data sheet of an nxp semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive sp ecifications and standards, customer (a) shall use the product without nx p semiconductors? warranty of the document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 77 of 79 nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
LPC2420_60_5 ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 05 ? 24 february 2010 78 of 79 continued >> nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 functional description . . . . . . . . . . . . . . . . . . 25 7.1 architectural overview . . . . . . . . . . . . . . . . . . 25 7.2 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 interrupt controller . . . . . . . . . . . . . . . . . . . . . 27 7.4.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 28 7.5 pin connect block . . . . . . . . . . . . . . . . . . . . . . 28 7.6 external memory controller. . . . . . . . . . . . . . . 28 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7 general purpose dma controller . . . . . . . . . . 29 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8 fast general purpose parallel i/o . . . . . . . . . . 30 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.9 ethernet (lpc2460 only) . . . . . . . . . . . . . . . . 31 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.10 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.10.1 usb device controller . . . . . . . . . . . . . . . . . . . 32 7.10.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.10.2 usb host controller. . . . . . . . . . . . . . . . . . . . . 32 7.10.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.10.3 usb otg controller . . . . . . . . . . . . . . . . . . . . 33 7.10.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.11 can controller and acceptance filters (lpc2460 only). . . . . . . . . . . . . . . . . . . . . . . . 33 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.12 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.13 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.14 uarts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.15 spi serial i/o controller. . . . . . . . . . . . . . . . . . 35 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.16 ssp serial i/o controller . . . . . . . . . . . . . . . . . 35 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.17 sd/mmc card interface . . . . . . . . . . . . . . . . . 35 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.18 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 36 7.18.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19 i 2 s-bus serial i/o controllers . . . . . . . . . . . . . 36 7.19.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.20 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 37 7.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.21 pulse width modulator . . . . . . . . . . . . . . . . . . 38 7.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.22 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 39 7.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.23 rtc and battery ram . . . . . . . . . . . . . . . . . . 39 7.23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.24 clocking and power control . . . . . . . . . . . . . . 40 7.24.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 40 7.24.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 40 7.24.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 40 7.24.1.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 41 7.24.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.24.3 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 41 7.24.4 power control . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.24.4.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.24.4.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.24.4.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 42 7.24.4.4 deep power-down mode . . . . . . . . . . . . . . . . 43 7.24.4.5 power domains . . . . . . . . . . . . . . . . . . . . . . . 43 7.25 system control . . . . . . . . . . . . . . . . . . . . . . . . 44 7.25.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.25.2 boot process . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.25.3 brownout detection . . . . . . . . . . . . . . . . . . . . 44 7.25.4 ahb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.25.5 external interrupt inputs . . . . . . . . . . . . . . . . . 45 7.25.6 memory mapping control . . . . . . . . . . . . . . . . 45 7.26 emulation and debugging . . . . . . . . . . . . . . . 45 7.26.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 45 7.26.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 46 7.26.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 47 9 static characteristics . . . . . . . . . . . . . . . . . . . 48 9.1 power-down mode . . . . . . . . . . . . . . . . . . . . . 51 9.2 deep power-down mode . . . . . . . . . . . . . . . . 52 10 dynamic characteristics. . . . . . . . . . . . . . . . . 54 10.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11 adc electrical characteristics . . . . . . . . . . . . 61 12 dac electrical characteristics . . . . . . . . . . . . 64 13 application information . . . . . . . . . . . . . . . . . 64 13.1 suggested usb interface solutions . . . . . . . . 64 13.2 xtal1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 69
nxp semiconductors LPC2420/2460 flashless 16-bit/32-b it microcontroller ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 february 2010 document identifier: LPC2420_60_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 13.3 xtal and rtc printed circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . 70 13.4 suggested boot memory interface solutions. . 70 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 75 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 76 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 76 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18 contact information. . . . . . . . . . . . . . . . . . . . . 77 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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